UVM testbench #110
Labels
assurance
Issues that relate to the assurance of the system, whether via models, code, informal, or formal.
cryptol
Issues related to our Cryptol specifications, or use thereof.
ENHANCEMENT
New feature or request
FEATURE
hardware
Q/A
Quality assurance issue; validation, testing, and formal assurance.
Someday
Issues that are not required by our current contract, but we'd like to attend to someday.
specifications
Issues that relate to system specifications, whether of models, code, protocols, or otherwise.
suggestion
verification
Milestone
Explore generating a UVM testbench from our Cryptol model. Such a testbench would translate Cryptol properties to UVM properties, which would in turn be validated through runtime verification on all hardware digital twins and the deployment platform as well as formally verified using yosys &c.
This is not a promised outcome of our project for the NRC. I have filed this issue for later IR&D.
The text was updated successfully, but these errors were encountered: