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riscv: avoid compressed instructions #2419

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@Arusekk Arusekk commented Jun 15, 2024

... and do not throw errors if there are relocs (might be benign)

@@ -267,8 +268,8 @@ def _assembler():
'ia64': [gas, '-m%ce' % context.endianness[0]],

# riscv64-unknown-elf-as supports riscv32 as well as riscv64
'riscv32': [gas, '-march=rv32gc', '-mabi=ilp32'],
'riscv64': [gas, '-march=rv64gc', '-mabi=lp64'],
'riscv32': [gas, '-march=rv32g', '-mabi=ilp32'],
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This prevents you from using compressed instructions when manually writing shellcode and compiling using asm, no?

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Sure, and therefore I am not very sure about this change. I don't know any way to avoid C and yet allow c.* opcodes.

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I think we thought about adding assembler command line args to context when adding riscv support? Or just asm?

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We could do this like we do with thumb (separate arch) but I doubt whether it is worth it. Maybe we can revisit this one day.

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Would it make sense to make two different archs? That way you could do asm -c riscv32 and asm -c riscv32c or something similar?

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Maybe add this as a context.subarch similar to what is requested for mips and arm? It's not really a sub-architecture though

@Arusekk Arusekk linked an issue Sep 5, 2024 that may be closed by this pull request
@@ -60,11 +60,11 @@ Example:
sd t4, -8(sp)
addi sp, sp, -8
>>> print(enhex(asm(shellcraft.riscv64.pushstr("/bin/sh"))))
b79e39349b8e7e7bb20e938ebe34b60e938efe22233cd1ff6111
b79e39349b8e7e7b939ece00938ebe34939ede00938efe22233cd1ff130181ff
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There's a new nullbyte here now

@Xeonacid
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I think including the C extension by default is reasonable.

All existing riscv64 chips designed to run Linux have the C extension, and main Linux distributions (Debian, Ubuntu, Fedora, Arch Linux...) all use rv64gc as their baseline. When users generate riscv64 shellcode using pwntools, they are most likely running it on a platform that includes the C extension.

Including the C extension by default also offers more possibilities for shellcode generation. As @peace-maker pointed out above, a shellcode without the C extension might introduce a null byte.

However, riscv32 deserves additional consideration, as it is commonly used in embedded systems where the C extension is not necessarily included.

Arusekk and others added 4 commits December 13, 2024 00:30
... and do not throw errors if there are relocs (might be benign)
@Arusekk Arusekk force-pushed the riscv-avoid-compressed branch from e83748b to 3ca6c61 Compare December 12, 2024 23:33
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Assembly seems to be broken on riscv
4 participants