From a59c8b08d549ca4a777a66df0471f15dbed5d299 Mon Sep 17 00:00:00 2001
From: Chris Copeland <chris@chrisnc.net>
Date: Thu, 15 Dec 2022 19:38:53 -0800
Subject: [PATCH] Add more interrupt priority asserts for ARM_CM3, ARM_CM4, and
 ARM_CM7

In the ARM_CM3, ARM_CM4, and ARM_CM7 ports, change the assertion that
configMAX_SYSCALL_INTERRUPT_PRIORITY is nonzero to account for the
number of priority bits implemented by the hardware, and add an
assertion that configKERNEL_INTERRUPT_PRIORITY is the maximum value,
also accounting for the supported priority bits.
---
 portable/GCC/ARM_CM3/port.c      | 16 ++++++++++++----
 portable/GCC/ARM_CM3_MPU/port.c  | 16 ++++++++++++----
 portable/GCC/ARM_CM4F/port.c     | 16 ++++++++++++----
 portable/GCC/ARM_CM4_MPU/port.c  | 16 ++++++++++++----
 portable/GCC/ARM_CM7/r0p1/port.c | 16 ++++++++++++----
 5 files changed, 60 insertions(+), 20 deletions(-)

diff --git a/portable/GCC/ARM_CM3/port.c b/portable/GCC/ARM_CM3/port.c
index 7f650fd360d..dc1d9ec2b27 100644
--- a/portable/GCC/ARM_CM3/port.c
+++ b/portable/GCC/ARM_CM3/port.c
@@ -265,10 +265,6 @@ static void prvPortStartFirstTask( void )
  */
 BaseType_t xPortStartScheduler( void )
 {
-    /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
-     * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
-    configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
-
     #if ( configASSERT_DEFINED == 1 )
     {
         volatile uint32_t ulOriginalPriority;
@@ -293,6 +289,18 @@ BaseType_t xPortStartScheduler( void )
         /* Use the same mask on the maximum system call priority. */
         ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
 
+        /* Check that the maximum system call priority is nonzero after
+         * accounting for the number of priority bits supported by the
+         * hardware. A priority of 0 is invalid because setting the BASEPRI
+         * register to 0 unmasks all interrupts, and interrupts with priority 0
+         * cannot be masked using BASEPRI.
+         * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+        configASSERT( ucMaxSysCallPriority );
+
+        /* Check that the interrupt priority used for PendSV and SysTick is the
+         * lowest supported by the hardware. */
+        configASSERT( (configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue) == ucMaxPriorityValue );
+
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
         ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
diff --git a/portable/GCC/ARM_CM3_MPU/port.c b/portable/GCC/ARM_CM3_MPU/port.c
index e0f1d170154..771c9e0d9c9 100644
--- a/portable/GCC/ARM_CM3_MPU/port.c
+++ b/portable/GCC/ARM_CM3_MPU/port.c
@@ -381,10 +381,6 @@ static void prvRestoreContextOfFirstTask( void )
  */
 BaseType_t xPortStartScheduler( void )
 {
-    /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See
-     * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
-    configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );
-
     #if ( configASSERT_DEFINED == 1 )
         {
             volatile uint32_t ulOriginalPriority;
@@ -409,6 +405,18 @@ BaseType_t xPortStartScheduler( void )
             /* Use the same mask on the maximum system call priority. */
             ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
 
+            /* Check that the maximum system call priority is nonzero after
+             * accounting for the number of priority bits supported by the
+             * hardware. A priority of 0 is invalid because setting the BASEPRI
+             * register to 0 unmasks all interrupts, and interrupts with priority 0
+             * cannot be masked using BASEPRI.
+             * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+            configASSERT( ucMaxSysCallPriority );
+
+            /* Check that the interrupt priority used for PendSV and SysTick is the
+             * lowest supported by the hardware. */
+            configASSERT( (configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue) == ucMaxPriorityValue );
+
             /* Calculate the maximum acceptable priority group value for the number
              * of bits read back. */
             ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
diff --git a/portable/GCC/ARM_CM4F/port.c b/portable/GCC/ARM_CM4F/port.c
index b946e6e9435..16f43d8e954 100644
--- a/portable/GCC/ARM_CM4F/port.c
+++ b/portable/GCC/ARM_CM4F/port.c
@@ -295,10 +295,6 @@ static void prvPortStartFirstTask( void )
  */
 BaseType_t xPortStartScheduler( void )
 {
-    /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
-     * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
-    configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
-
     /* This port can be used on all revisions of the Cortex-M7 core other than
      * the r0p1 parts.  r0p1 parts should use the port from the
      * /source/portable/GCC/ARM_CM7/r0p1 directory. */
@@ -329,6 +325,18 @@ BaseType_t xPortStartScheduler( void )
         /* Use the same mask on the maximum system call priority. */
         ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
 
+        /* Check that the maximum system call priority is nonzero after
+         * accounting for the number of priority bits supported by the
+         * hardware. A priority of 0 is invalid because setting the BASEPRI
+         * register to 0 unmasks all interrupts, and interrupts with priority 0
+         * cannot be masked using BASEPRI.
+         * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+        configASSERT( ucMaxSysCallPriority );
+
+        /* Check that the interrupt priority used for PendSV and SysTick is the
+         * lowest supported by the hardware. */
+        configASSERT( (configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue) == ucMaxPriorityValue );
+
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
         ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
diff --git a/portable/GCC/ARM_CM4_MPU/port.c b/portable/GCC/ARM_CM4_MPU/port.c
index 3125f7824d4..d11c4c3f6b3 100644
--- a/portable/GCC/ARM_CM4_MPU/port.c
+++ b/portable/GCC/ARM_CM4_MPU/port.c
@@ -412,10 +412,6 @@ static void prvRestoreContextOfFirstTask( void )
  */
 BaseType_t xPortStartScheduler( void )
 {
-    /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See
-     * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
-    configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );
-
     /* Errata 837070 workaround must only be enabled on Cortex-M7 r0p0
      * and r0p1 cores. */
     #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
@@ -452,6 +448,18 @@ BaseType_t xPortStartScheduler( void )
             /* Use the same mask on the maximum system call priority. */
             ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
 
+            /* Check that the maximum system call priority is nonzero after
+             * accounting for the number of priority bits supported by the
+             * hardware. A priority of 0 is invalid because setting the BASEPRI
+             * register to 0 unmasks all interrupts, and interrupts with priority 0
+             * cannot be masked using BASEPRI.
+             * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+            configASSERT( ucMaxSysCallPriority );
+
+            /* Check that the interrupt priority used for PendSV and SysTick is the
+             * lowest supported by the hardware. */
+            configASSERT( (configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue) == ucMaxPriorityValue );
+
             /* Calculate the maximum acceptable priority group value for the number
              * of bits read back. */
             ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
diff --git a/portable/GCC/ARM_CM7/r0p1/port.c b/portable/GCC/ARM_CM7/r0p1/port.c
index a9c69aae7fa..bd89e5bdb2e 100644
--- a/portable/GCC/ARM_CM7/r0p1/port.c
+++ b/portable/GCC/ARM_CM7/r0p1/port.c
@@ -289,10 +289,6 @@ static void prvPortStartFirstTask( void )
  */
 BaseType_t xPortStartScheduler( void )
 {
-    /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
-     * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
-    configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
-
     #if ( configASSERT_DEFINED == 1 )
     {
         volatile uint32_t ulOriginalPriority;
@@ -317,6 +313,18 @@ BaseType_t xPortStartScheduler( void )
         /* Use the same mask on the maximum system call priority. */
         ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
 
+        /* Check that the maximum system call priority is nonzero after
+         * accounting for the number of priority bits supported by the
+         * hardware. A priority of 0 is invalid because setting the BASEPRI
+         * register to 0 unmasks all interrupts, and interrupts with priority 0
+         * cannot be masked using BASEPRI.
+         * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+        configASSERT( ucMaxSysCallPriority );
+
+        /* Check that the interrupt priority used for PendSV and SysTick is the
+         * lowest supported by the hardware. */
+        configASSERT( (configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue) == ucMaxPriorityValue );
+
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
         ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;