diff --git a/app/resources/boards/FleaFPGA-Ohm_(FT2232H)/FleaFPGA_Ohm.pdf b/app/resources/boards/FleaFPGA-Ohm_(FT2232H)/FleaFPGA_Ohm.pdf new file mode 100644 index 000000000..5eac41b90 Binary files /dev/null and b/app/resources/boards/FleaFPGA-Ohm_(FT2232H)/FleaFPGA_Ohm.pdf differ diff --git a/app/resources/boards/FleaFPGA-Ohm_(FT2232H)/JTAG_connector.png b/app/resources/boards/FleaFPGA-Ohm_(FT2232H)/JTAG_connector.png new file mode 100644 index 000000000..29b8174cf Binary files /dev/null and b/app/resources/boards/FleaFPGA-Ohm_(FT2232H)/JTAG_connector.png differ diff --git a/app/resources/boards/FleaFPGA-Ohm_(FT2232H)/_____pinout.lpf b/app/resources/boards/FleaFPGA-Ohm_(FT2232H)/_____pinout.lpf new file mode 100644 index 000000000..b86f80c6f --- /dev/null +++ b/app/resources/boards/FleaFPGA-Ohm_(FT2232H)/_____pinout.lpf @@ -0,0 +1,214 @@ +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +## FleaFPGA_Ohm_A5 Pin Constraints File +## Author: Valentin Angelovski +## Date: 15th January 2018 +## +## ***** ECP5 PIN DECLARATIONS ***** +## USER LED; +IOBUF PORT "n_led1" PULLMODE=NONE IO_TYPE=LVCMOS25 ; +LOCATE COMP "n_led1" SITE "P2" ; +## USB SLAVE UART; ## Swapped in PCB rev 2v4!!! +IOBUF PORT "slave_rx_i" IO_TYPE=LVCMOS25 PULLMODE=NONE ; +IOBUF PORT "slave_tx_o" IO_TYPE=LVCMOS25 ; +IOBUF PORT "slave_cts_i" IO_TYPE=LVCMOS25 PULLMODE=NONE ; +LOCATE COMP "slave_tx_o" SITE "P1" ; +LOCATE COMP "slave_rx_i" SITE "P3" ; +LOCATE COMP "slave_cts_i" SITE "Y2" ; +## 25MHz MASTER CLOCK AND RESET; +IOBUF PORT "sys_clock" IO_TYPE=LVCMOS25 ; +FREQUENCY PORT "sys_clock" 25.000000 MHz ; +IOBUF PORT "sys_reset" PULLMODE=UP IO_TYPE=LVCMOS33 ; +LOCATE COMP "sys_reset" SITE "T17" ; +LOCATE COMP "sys_clock" SITE "H2" ; +## IOBUF PS/2 AND USB HOST PORTS +IOBUF PORT "PS2_clk1" IO_TYPE=LVCMOS25 PULLMODE=UP ; +IOBUF PORT "PS2_data1" IO_TYPE=LVCMOS25 PULLMODE=UP ; +LOCATE COMP "PS2_clk1" SITE "K2" ; +LOCATE COMP "PS2_data1" SITE "J1" ; +IOBUF PORT "PS2_clk2" PULLMODE=UP IO_TYPE=LVCMOS25 ; +IOBUF PORT "PS2_data2" PULLMODE=UP IO_TYPE=LVCMOS25 ; +LOCATE COMP "PS2_clk2" SITE "N2" ; +LOCATE COMP "PS2_data2" SITE "M1" ; +IOBUF PORT "PS2_enable" IO_TYPE=LVCMOS25 PULLMODE=NONE ; +LOCATE COMP "PS2_enable" SITE "N1" ; +## IOBUF RASPI COMPATIBLE GPIO HEADER +## NOTE: GPIO_5, GPIO_7, GPIO_10 AND GPIO_24 MUST ALL BE COMMENTED OUT WHEN USING THESE PINS AS SIGMA DELTA ADC INPUTS! +IOBUF PORT "GPIO_2" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "GPIO_3" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "GPIO_4" IO_TYPE=LVCMOS33 ; +IOBUF PORT "GPIO_17" IO_TYPE=LVCMOS33 ; +IOBUF PORT "GPIO_27" IO_TYPE=LVCMOS33 ; +IOBUF PORT "GPIO_22" IO_TYPE=LVCMOS33 ; +IOBUF PORT "GPIO_10" IO_TYPE=LVCMOS33 ; +IOBUF PORT "GPIO_9" IO_TYPE=LVCMOS33 ; +IOBUF PORT "GPIO_11" IO_TYPE=LVCMOS33 ; +IOBUF PORT "GPIO_IDSD" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "GPIO_5" IO_TYPE=LVCMOS33 ; +IOBUF PORT "GPIO_6" IO_TYPE=LVCMOS33 ; +IOBUF PORT "GPIO_13" IO_TYPE=LVCMOS33 ; +IOBUF PORT "GPIO_19" IO_TYPE=LVCMOS33 ; +IOBUF PORT "GPIO_26" IO_TYPE=LVCMOS33 ; +IOBUF PORT "GPIO_14" IO_TYPE=LVCMOS33 ; +IOBUF PORT "GPIO_15" IO_TYPE=LVCMOS33 ; +IOBUF PORT "GPIO_18" IO_TYPE=LVCMOS33 ; +IOBUF PORT "GPIO_23" IO_TYPE=LVCMOS33 ; +IOBUF PORT "GPIO_24" IO_TYPE=LVCMOS33 ; +IOBUF PORT "GPIO_25" IO_TYPE=LVCMOS33 ; +IOBUF PORT "GPIO_8" IO_TYPE=LVCMOS33 ; +IOBUF PORT "GPIO_7" IO_TYPE=LVCMOS33 ; +IOBUF PORT "GPIO_IDSC" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "GPIO_12" IO_TYPE=LVCMOS33 ; +IOBUF PORT "GPIO_16" IO_TYPE=LVCMOS33 ; +IOBUF PORT "GPIO_20" IO_TYPE=LVCMOS33 ; +IOBUF PORT "GPIO_21" IO_TYPE=LVCMOS33 ; +LOCATE COMP "GPIO_2" SITE "D17" ; +LOCATE COMP "GPIO_3" SITE "C18" ; +LOCATE COMP "GPIO_4" SITE "D19" ; +LOCATE COMP "GPIO_17" SITE "F17" ; +LOCATE COMP "GPIO_27" SITE "G18" ; +LOCATE COMP "GPIO_22" SITE "F19" ; +LOCATE COMP "GPIO_10" SITE "G19" ; +LOCATE COMP "GPIO_9" SITE "J19" ; +LOCATE COMP "GPIO_11" SITE "K19" ; +LOCATE COMP "GPIO_IDSD" SITE "N19" ; +LOCATE COMP "GPIO_5" SITE "T20" ; +LOCATE COMP "GPIO_6" SITE "T19" ; +LOCATE COMP "GPIO_13" SITE "N16" ; +LOCATE COMP "GPIO_19" SITE "U18" ; +LOCATE COMP "GPIO_26" SITE "U17" ; +LOCATE COMP "GPIO_14" SITE "C20" ; +LOCATE COMP "GPIO_15" SITE "E17" ; +LOCATE COMP "GPIO_18" SITE "D18" ; +LOCATE COMP "GPIO_23" SITE "E20" ; +LOCATE COMP "GPIO_24" SITE "D20" ; +LOCATE COMP "GPIO_25" SITE "L20" ; +LOCATE COMP "GPIO_8" SITE "M20" ; +LOCATE COMP "GPIO_7" SITE "L19" ; +LOCATE COMP "GPIO_IDSC" SITE "N20" ; +LOCATE COMP "GPIO_12" SITE "R18" ; +LOCATE COMP "GPIO_16" SITE "M17" ; +LOCATE COMP "GPIO_20" SITE "N17" ; +LOCATE COMP "GPIO_21" SITE "P16" ; +## +## SIGMA-DELTA ADC INPUTS +## NOTE: THESE PIN DEFINITIONS MUST BE COMMENTED OUT WHEN GPIO_5, GPIO_7, GPIO_10 AND GPIO_24 USED AS PLAIN OLD DIGITAL GPIO! +##IOBUF PORT "ADC3_error" IO_TYPE=LVCMOS33 ; +##LOCATE COMP "ADC3_error" SITE "R20" ; +##IOBUF PORT "ADC3_input" IO_TYPE=LVCMOS33D PULLMODE=NONE ; +##LOCATE COMP "ADC3_input" SITE "T20" ; +##LOCATE COMP "ADC2_error" SITE "P20" ; +##IOBUF PORT "ADC2_error" IO_TYPE=LVCMOS33 ; +##IOBUF PORT "ADC2_input" PULLMODE=NONE IO_TYPE=LVCMOS33D ; +##LOCATE COMP "ADC2_input" SITE "L19" ; +##IOBUF PORT "ADC1_error" IO_TYPE=LVCMOS33 ; +#IOBUF PORT "ADC1_input" IO_TYPE=LVCMOS33D ; +##LOCATE COMP "ADC1_input" SITE "G19" ; +##LOCATE COMP "ADC1_error" SITE "J20" ; +##IOBUF PORT "ADC0_input" PULLMODE=NONE IO_TYPE=LVCMOS33D ; +##IOBUF PORT "ADC0_error" IO_TYPE=LVCMOS33 ; +##LOCATE COMP "ADC0_error" SITE "E18" ; +##LOCATE COMP "ADC0_input" SITE "D20" ; +## +## SDRAM; +IOBUF PORT "Dram_Clk" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_n_Ras" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_CKE" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_n_Cas" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_n_We" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_n_cs" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_DQMH" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_DQML" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_BA[0]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_BA[1]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Addr[12]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Addr[11]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Addr[10]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Addr[9]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Addr[8]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Addr[7]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Addr[6]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Addr[5]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Addr[4]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Addr[3]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Addr[2]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Addr[1]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Addr[0]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Data[15]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Data[14]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Data[13]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Data[12]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Data[11]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Data[10]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Data[9]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Data[8]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Data[7]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Data[6]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Data[5]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Data[4]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Data[3]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Data[2]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Data[1]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Data[0]" IO_TYPE=LVCMOS33 ; +LOCATE COMP "Dram_Addr[0]" SITE "B12" ; +LOCATE COMP "Dram_Addr[3]" SITE "A13" ; +LOCATE COMP "Dram_BA[0]" SITE "A12" ; +LOCATE COMP "Dram_BA[1]" SITE "D11" ; +LOCATE COMP "Dram_CKE" SITE "C15" ; +LOCATE COMP "Dram_Clk" SITE "C17" ; +LOCATE COMP "Dram_Addr[1]" SITE "C10" ; +LOCATE COMP "Dram_Addr[2]" SITE "D8" ; +LOCATE COMP "Dram_Addr[4]" SITE "D13" ; +LOCATE COMP "Dram_Addr[5]" SITE "C13" ; +LOCATE COMP "Dram_Addr[6]" SITE "B13" ; +LOCATE COMP "Dram_Addr[7]" SITE "D15" ; +LOCATE COMP "Dram_Addr[8]" SITE "D14" ; +LOCATE COMP "Dram_Addr[9]" SITE "A14" ; +LOCATE COMP "Dram_Addr[11]" SITE "C16" ; +LOCATE COMP "Dram_Addr[12]" SITE "C14" ; +LOCATE COMP "Dram_Addr[10]" SITE "D9" ; +LOCATE COMP "Dram_DQMH" SITE "D16" ; +LOCATE COMP "Dram_DQML" SITE "A11" ; +LOCATE COMP "Dram_n_Cas" SITE "B11" ; +LOCATE COMP "Dram_n_Ras" SITE "C12" ; +LOCATE COMP "Dram_n_We" SITE "D12" ; +LOCATE COMP "Dram_n_cs" SITE "C11" ; +LOCATE COMP "Dram_Data[0]" SITE "A10" ; +LOCATE COMP "Dram_Data[1]" SITE "B9" ; +LOCATE COMP "Dram_Data[2]" SITE "B10" ; +LOCATE COMP "Dram_Data[3]" SITE "A9" ; +LOCATE COMP "Dram_Data[4]" SITE "B8" ; +LOCATE COMP "Dram_Data[5]" SITE "A8" ; +LOCATE COMP "Dram_Data[6]" SITE "C8" ; +LOCATE COMP "Dram_Data[7]" SITE "A7" ; +LOCATE COMP "Dram_Data[8]" SITE "A19" ; +LOCATE COMP "Dram_Data[9]" SITE "B18" ; +LOCATE COMP "Dram_Data[10]" SITE "A18" ; +LOCATE COMP "Dram_Data[11]" SITE "B17" ; +LOCATE COMP "Dram_Data[12]" SITE "A17" ; +LOCATE COMP "Dram_Data[13]" SITE "B15" ; +LOCATE COMP "Dram_Data[14]" SITE "B16" ; +LOCATE COMP "Dram_Data[15]" SITE "A16" ; +## SD/MMC PORT +IOBUF PORT "mmc_miso" IO_TYPE=LVCMOS25 PULLMODE=NONE ; +IOBUF PORT "mmc_dat1" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "mmc_dat2" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "mmc_n_cs" IO_TYPE=LVCMOS25 PULLMODE=NONE ; +IOBUF PORT "mmc_mosi" IO_TYPE=LVCMOS25 PULLMODE=NONE ; +IOBUF PORT "mmc_clk" IO_TYPE=LVCMOS25 ; +LOCATE COMP "mmc_miso" SITE "C2" ; +LOCATE COMP "mmc_clk" SITE "C3" ; +LOCATE COMP "mmc_mosi" SITE "B2" ; +LOCATE COMP "mmc_n_cs" SITE "B3" ; +## SYSCONFIG PARAMETERS +VCCIO_DERATE PERCENT 0; +SYSCONFIG CONFIG_IOVOLTAGE=3.3 SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=ENABLE SLAVE_PARALLEL_PORT=DISABLE BACKGROUND_RECONFIG=OFF TRANSFR=ON CONFIG_MODE=SPI_SERIAL DONE_OD=OFF DONE_EX=OFF MCCLK_FREQ=38.8 ; +## DIGITAL VIDEO OUT +IOBUF PORT "LVDS_Blue[0]" IO_TYPE=LVDS ; +IOBUF PORT "LVDS_Green[0]" IO_TYPE=LVDS ; +IOBUF PORT "LVDS_Red[0]" IO_TYPE=LVDS ; +IOBUF PORT "LVDS_ck[0]" IO_TYPE=LVDS ; +LOCATE COMP "LVDS_Red[0]" SITE "C1" ; +LOCATE COMP "LVDS_Blue[0]" SITE "A4" ; +LOCATE COMP "LVDS_Green[0]" SITE "A2" ; +LOCATE COMP "LVDS_ck[0]" SITE "G2" ; diff --git a/app/resources/boards/FleaFPGA-Ohm_(FT2232H)/info.json b/app/resources/boards/FleaFPGA-Ohm_(FT2232H)/info.json new file mode 100644 index 000000000..b23192ff4 --- /dev/null +++ b/app/resources/boards/FleaFPGA-Ohm_(FT2232H)/info.json @@ -0,0 +1 @@ +{"label":"FleaFPGA-Ohm_(FT2232H)","datasheet":"https://github.com/Basman74/FleaFPGA-Ohm","interface":"FTDI","arch":"ecp5","FPGAResources":{"ffs":24288,"luts":24288,"pios":96,"plbs":660,"brams":30}} \ No newline at end of file diff --git a/app/resources/boards/FleaFPGA-Ohm_(FT2232H)/pinout.json b/app/resources/boards/FleaFPGA-Ohm_(FT2232H)/pinout.json new file mode 100644 index 000000000..047308c52 --- /dev/null +++ b/app/resources/boards/FleaFPGA-Ohm_(FT2232H)/pinout.json @@ -0,0 +1,110 @@ +[ +{"type":"input","name":"CLK","value":"H2"}, +{"type":"input","name":"Reset","value":"T17","pullmode":"UP"}, + +{"type":"output","name":"LED","value":"P2","pullmode":"NONE"}, + +{"type":"output","name":"slave_rx_i","value":"P1","pullmode":"NONE"}, +{"type":"input","name":"slave_tx_o","value":"P3"}, +{"type":"output","name":"slave_cts_i","value":"Y2","pullmode":"NONE"}, + +{"type":"input","name":"Button","value":"M13","pullmode":"NONE"}, + +{"type":"inout","name":"GPIO_IDSD","value":"N19","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_IDSC","value":"N20","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_2","value":"D17","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_3","value":"C18","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_4","value":"D19","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_5","value":"T20","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_6","value":"T19","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_7","value":"L19","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_8","value":"M20","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_9","value":"J19","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_10","value":"G19","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_11","value":"K19","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_12","value":"R18","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_13","value":"N16","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_14","value":"C20","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_15","value":"E17","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_16","value":"M17","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_17","value":"F17","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_18","value":"D18","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_19","value":"U18","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_20","value":"N17","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_21","value":"P16","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_22","value":"F19","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_23","value":"E20","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_24","value":"D20","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_25","value":"L20","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_26","value":"U17","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_27","value":"G18","pullmode":"NONE"}, + +{"type":"output","name":"sdram_clk","value":"C17","pullmode":"NONE"}, +{"type":"output","name":"sdram_cke","value":"C15","pullmode":"NONE"}, +{"type":"output","name":"sdram_wen","value":"D12","pullmode":"NONE"}, +{"type":"output","name":"sdram_rasn","value":"C12","pullmode":"NONE"}, +{"type":"output","name":"sdram_casn","value":"B11","pullmode":"NONE"}, +{"type":"output","name":"sdram_BA[0]","value":"A12","pullmode":"NONE"}, +{"type":"output","name":"sdram_BA[1]","value":"D11","pullmode":"NONE"}, +{"type":"output","name":"sdram_DQMH","value":"D16","pullmode":"NONE"}, +{"type":"output","name":"sdram_DQML","value":"A11","pullmode":"NONE"}, + +{"type":"output","name":"sdram_a0","value":"B12","pullmode":"NONE"}, +{"type":"output","name":"sdram_a1","value":"C10","pullmode":"NONE"}, +{"type":"output","name":"sdram_a2","value":"D8","pullmode":"NONE"}, +{"type":"output","name":"sdram_a3","value":"A13","pullmode":"NONE"}, +{"type":"output","name":"sdram_a4","value":"D13","pullmode":"NONE"}, +{"type":"output","name":"sdram_a5","value":"C13","pullmode":"NONE"}, +{"type":"output","name":"sdram_a6","value":"B13","pullmode":"NONE"}, +{"type":"output","name":"sdram_a7","value":"D15","pullmode":"NONE"}, +{"type":"output","name":"sdram_a8","value":"D14","pullmode":"NONE"}, +{"type":"output","name":"sdram_a9","value":"A14","pullmode":"NONE"}, +{"type":"output","name":"sdram_a10","value":"D9","pullmode":"NONE"}, +{"type":"output","name":"sdram_a11","value":"C16","pullmode":"NONE"}, +{"type":"output","name":"sdram_a12","value":"C14","pullmode":"NONE"}, + +{"type":"inout","name":"sdram_d0","value":"A10","pullmode":"NONE"}, +{"type":"inout","name":"sdram_d1","value":"B9","pullmode":"NONE"}, +{"type":"inout","name":"sdram_d2","value":"B10","pullmode":"NONE"}, +{"type":"inout","name":"sdram_d3","value":"A9","pullmode":"NONE"}, +{"type":"inout","name":"sdram_d4","value":"B8","pullmode":"NONE"}, +{"type":"inout","name":"sdram_d5","value":"A8","pullmode":"NONE"}, +{"type":"inout","name":"sdram_d6","value":"C8","pullmode":"NONE"}, +{"type":"inout","name":"sdram_d7","value":"A7","pullmode":"NONE"}, +{"type":"inout","name":"sdram_d8","value":"A19","pullmode":"NONE"}, +{"type":"inout","name":"sdram_d9","value":"B18","pullmode":"NONE"}, +{"type":"inout","name":"sdram_d10","value":"A18","pullmode":"NONE"}, +{"type":"inout","name":"sdram_d11","value":"B17","pullmode":"NONE"}, +{"type":"inout","name":"sdram_d12","value":"A17","pullmode":"NONE"}, +{"type":"inout","name":"sdram_d13","value":"B15","pullmode":"NONE"}, +{"type":"inout","name":"sdram_d14","value":"B16","pullmode":"NONE"}, +{"type":"inout","name":"sdram_d15","value":"A16","pullmode":"NONE"}, + +{"type":"output","name":"SD_Clk","value":"C3","pullmode":"NONE"}, +{"type":"output","name":"SD_n_CS","value":"B3","pullmode":"NONE"}, +{"type":"input","name":"SD_Miso","value":"C2","pullmode":"NONE"}, +{"type":"output","name":"SD_Mosi","value":"B2","pullmode":"NONE"}, +{"type":"inout","name":"SD_Dat1","value":"A3","pullmode":"NONE"}, +{"type":"inout","name":"SD_Dat2","value":"E1","pullmode":"NONE"}, + +{"type":"output","name":"SPI_Clk","value":"U3","pullmode":"NONE"}, +{"type":"output","name":"SPI_n_CS","value":"R2","pullmode":"NONE"}, +{"type":"input","name":"SPI_Miso","value":"V2","pullmode":"NONE"}, +{"type":"output","name":"SPI_Mosi","value":"W2","pullmode":"NONE"}, + +{"type":"inout","name":"PS2_clk1","value":"K2","pullmode":"UP"}, +{"type":"inout","name":"PS2_data1","value":"J1","pullmode":"UP"}, +{"type":"inout","name":"PS2_clk2","value":"N2","pullmode":"UP"}, +{"type":"inout","name":"PS2_data2","value":"M1","pullmode":"UP"}, +{"type":"input","name":"PS2_enable","value":"N1","pullmode":"UP"}, + +{"type":"output","name":"D2_Pos","value":"C1","pullmode":"NONE"}, +{"type":"output","name":"D2_Neg","value":"D1","pullmode":"NONE"}, +{"type":"output","name":"D1_Pos","value":"A2","pullmode":"NONE"}, +{"type":"output","name":"D1_Neg","value":"B1","pullmode":"NONE"}, +{"type":"output","name":"D0_Pos","value":"A4","pullmode":"NONE"}, +{"type":"output","name":"D0_Neg","value":"A5","pullmode":"NONE"}, +{"type":"output","name":"CK_Pos","value":"G2","pullmode":"NONE"}, +{"type":"output","name":"CK_Neg","value":"F1","pullmode":"NONE"} + +] \ No newline at end of file diff --git a/app/resources/boards/FleaFPGA-Ohm_(FT2232H)/rules.json b/app/resources/boards/FleaFPGA-Ohm_(FT2232H)/rules.json new file mode 100644 index 000000000..a066ec476 --- /dev/null +++ b/app/resources/boards/FleaFPGA-Ohm_(FT2232H)/rules.json @@ -0,0 +1 @@ +{"input":[{"port":"clk","pin":"H2"}]} \ No newline at end of file diff --git a/app/resources/boards/FleaFPGA-Ohm_(FT232H)/FleaFPGA_Ohm.pdf b/app/resources/boards/FleaFPGA-Ohm_(FT232H)/FleaFPGA_Ohm.pdf new file mode 100644 index 000000000..5eac41b90 Binary files /dev/null and b/app/resources/boards/FleaFPGA-Ohm_(FT232H)/FleaFPGA_Ohm.pdf differ diff --git a/app/resources/boards/FleaFPGA-Ohm_(FT232H)/JTAG_connector.png b/app/resources/boards/FleaFPGA-Ohm_(FT232H)/JTAG_connector.png new file mode 100644 index 000000000..29b8174cf Binary files /dev/null and b/app/resources/boards/FleaFPGA-Ohm_(FT232H)/JTAG_connector.png differ diff --git a/app/resources/boards/FleaFPGA-Ohm_(FT232H)/_____pinout.lpf b/app/resources/boards/FleaFPGA-Ohm_(FT232H)/_____pinout.lpf new file mode 100644 index 000000000..b86f80c6f --- /dev/null +++ b/app/resources/boards/FleaFPGA-Ohm_(FT232H)/_____pinout.lpf @@ -0,0 +1,214 @@ +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +## FleaFPGA_Ohm_A5 Pin Constraints File +## Author: Valentin Angelovski +## Date: 15th January 2018 +## +## ***** ECP5 PIN DECLARATIONS ***** +## USER LED; +IOBUF PORT "n_led1" PULLMODE=NONE IO_TYPE=LVCMOS25 ; +LOCATE COMP "n_led1" SITE "P2" ; +## USB SLAVE UART; ## Swapped in PCB rev 2v4!!! +IOBUF PORT "slave_rx_i" IO_TYPE=LVCMOS25 PULLMODE=NONE ; +IOBUF PORT "slave_tx_o" IO_TYPE=LVCMOS25 ; +IOBUF PORT "slave_cts_i" IO_TYPE=LVCMOS25 PULLMODE=NONE ; +LOCATE COMP "slave_tx_o" SITE "P1" ; +LOCATE COMP "slave_rx_i" SITE "P3" ; +LOCATE COMP "slave_cts_i" SITE "Y2" ; +## 25MHz MASTER CLOCK AND RESET; +IOBUF PORT "sys_clock" IO_TYPE=LVCMOS25 ; +FREQUENCY PORT "sys_clock" 25.000000 MHz ; +IOBUF PORT "sys_reset" PULLMODE=UP IO_TYPE=LVCMOS33 ; +LOCATE COMP "sys_reset" SITE "T17" ; +LOCATE COMP "sys_clock" SITE "H2" ; +## IOBUF PS/2 AND USB HOST PORTS +IOBUF PORT "PS2_clk1" IO_TYPE=LVCMOS25 PULLMODE=UP ; +IOBUF PORT "PS2_data1" IO_TYPE=LVCMOS25 PULLMODE=UP ; +LOCATE COMP "PS2_clk1" SITE "K2" ; +LOCATE COMP "PS2_data1" SITE "J1" ; +IOBUF PORT "PS2_clk2" PULLMODE=UP IO_TYPE=LVCMOS25 ; +IOBUF PORT "PS2_data2" PULLMODE=UP IO_TYPE=LVCMOS25 ; +LOCATE COMP "PS2_clk2" SITE "N2" ; +LOCATE COMP "PS2_data2" SITE "M1" ; +IOBUF PORT "PS2_enable" IO_TYPE=LVCMOS25 PULLMODE=NONE ; +LOCATE COMP "PS2_enable" SITE "N1" ; +## IOBUF RASPI COMPATIBLE GPIO HEADER +## NOTE: GPIO_5, GPIO_7, GPIO_10 AND GPIO_24 MUST ALL BE COMMENTED OUT WHEN USING THESE PINS AS SIGMA DELTA ADC INPUTS! +IOBUF PORT "GPIO_2" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "GPIO_3" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "GPIO_4" IO_TYPE=LVCMOS33 ; +IOBUF PORT "GPIO_17" IO_TYPE=LVCMOS33 ; +IOBUF PORT "GPIO_27" IO_TYPE=LVCMOS33 ; +IOBUF PORT "GPIO_22" IO_TYPE=LVCMOS33 ; +IOBUF PORT "GPIO_10" IO_TYPE=LVCMOS33 ; +IOBUF PORT "GPIO_9" IO_TYPE=LVCMOS33 ; +IOBUF PORT "GPIO_11" IO_TYPE=LVCMOS33 ; +IOBUF PORT "GPIO_IDSD" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "GPIO_5" IO_TYPE=LVCMOS33 ; +IOBUF PORT "GPIO_6" IO_TYPE=LVCMOS33 ; +IOBUF PORT "GPIO_13" IO_TYPE=LVCMOS33 ; +IOBUF PORT "GPIO_19" IO_TYPE=LVCMOS33 ; +IOBUF PORT "GPIO_26" IO_TYPE=LVCMOS33 ; +IOBUF PORT "GPIO_14" IO_TYPE=LVCMOS33 ; +IOBUF PORT "GPIO_15" IO_TYPE=LVCMOS33 ; +IOBUF PORT "GPIO_18" IO_TYPE=LVCMOS33 ; +IOBUF PORT "GPIO_23" IO_TYPE=LVCMOS33 ; +IOBUF PORT "GPIO_24" IO_TYPE=LVCMOS33 ; +IOBUF PORT "GPIO_25" IO_TYPE=LVCMOS33 ; +IOBUF PORT "GPIO_8" IO_TYPE=LVCMOS33 ; +IOBUF PORT "GPIO_7" IO_TYPE=LVCMOS33 ; +IOBUF PORT "GPIO_IDSC" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "GPIO_12" IO_TYPE=LVCMOS33 ; +IOBUF PORT "GPIO_16" IO_TYPE=LVCMOS33 ; +IOBUF PORT "GPIO_20" IO_TYPE=LVCMOS33 ; +IOBUF PORT "GPIO_21" IO_TYPE=LVCMOS33 ; +LOCATE COMP "GPIO_2" SITE "D17" ; +LOCATE COMP "GPIO_3" SITE "C18" ; +LOCATE COMP "GPIO_4" SITE "D19" ; +LOCATE COMP "GPIO_17" SITE "F17" ; +LOCATE COMP "GPIO_27" SITE "G18" ; +LOCATE COMP "GPIO_22" SITE "F19" ; +LOCATE COMP "GPIO_10" SITE "G19" ; +LOCATE COMP "GPIO_9" SITE "J19" ; +LOCATE COMP "GPIO_11" SITE "K19" ; +LOCATE COMP "GPIO_IDSD" SITE "N19" ; +LOCATE COMP "GPIO_5" SITE "T20" ; +LOCATE COMP "GPIO_6" SITE "T19" ; +LOCATE COMP "GPIO_13" SITE "N16" ; +LOCATE COMP "GPIO_19" SITE "U18" ; +LOCATE COMP "GPIO_26" SITE "U17" ; +LOCATE COMP "GPIO_14" SITE "C20" ; +LOCATE COMP "GPIO_15" SITE "E17" ; +LOCATE COMP "GPIO_18" SITE "D18" ; +LOCATE COMP "GPIO_23" SITE "E20" ; +LOCATE COMP "GPIO_24" SITE "D20" ; +LOCATE COMP "GPIO_25" SITE "L20" ; +LOCATE COMP "GPIO_8" SITE "M20" ; +LOCATE COMP "GPIO_7" SITE "L19" ; +LOCATE COMP "GPIO_IDSC" SITE "N20" ; +LOCATE COMP "GPIO_12" SITE "R18" ; +LOCATE COMP "GPIO_16" SITE "M17" ; +LOCATE COMP "GPIO_20" SITE "N17" ; +LOCATE COMP "GPIO_21" SITE "P16" ; +## +## SIGMA-DELTA ADC INPUTS +## NOTE: THESE PIN DEFINITIONS MUST BE COMMENTED OUT WHEN GPIO_5, GPIO_7, GPIO_10 AND GPIO_24 USED AS PLAIN OLD DIGITAL GPIO! +##IOBUF PORT "ADC3_error" IO_TYPE=LVCMOS33 ; +##LOCATE COMP "ADC3_error" SITE "R20" ; +##IOBUF PORT "ADC3_input" IO_TYPE=LVCMOS33D PULLMODE=NONE ; +##LOCATE COMP "ADC3_input" SITE "T20" ; +##LOCATE COMP "ADC2_error" SITE "P20" ; +##IOBUF PORT "ADC2_error" IO_TYPE=LVCMOS33 ; +##IOBUF PORT "ADC2_input" PULLMODE=NONE IO_TYPE=LVCMOS33D ; +##LOCATE COMP "ADC2_input" SITE "L19" ; +##IOBUF PORT "ADC1_error" IO_TYPE=LVCMOS33 ; +#IOBUF PORT "ADC1_input" IO_TYPE=LVCMOS33D ; +##LOCATE COMP "ADC1_input" SITE "G19" ; +##LOCATE COMP "ADC1_error" SITE "J20" ; +##IOBUF PORT "ADC0_input" PULLMODE=NONE IO_TYPE=LVCMOS33D ; +##IOBUF PORT "ADC0_error" IO_TYPE=LVCMOS33 ; +##LOCATE COMP "ADC0_error" SITE "E18" ; +##LOCATE COMP "ADC0_input" SITE "D20" ; +## +## SDRAM; +IOBUF PORT "Dram_Clk" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_n_Ras" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_CKE" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_n_Cas" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_n_We" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_n_cs" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_DQMH" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_DQML" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_BA[0]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_BA[1]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Addr[12]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Addr[11]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Addr[10]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Addr[9]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Addr[8]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Addr[7]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Addr[6]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Addr[5]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Addr[4]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Addr[3]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Addr[2]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Addr[1]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Addr[0]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Data[15]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Data[14]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Data[13]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Data[12]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Data[11]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Data[10]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Data[9]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Data[8]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Data[7]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Data[6]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Data[5]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Data[4]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Data[3]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Data[2]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Data[1]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dram_Data[0]" IO_TYPE=LVCMOS33 ; +LOCATE COMP "Dram_Addr[0]" SITE "B12" ; +LOCATE COMP "Dram_Addr[3]" SITE "A13" ; +LOCATE COMP "Dram_BA[0]" SITE "A12" ; +LOCATE COMP "Dram_BA[1]" SITE "D11" ; +LOCATE COMP "Dram_CKE" SITE "C15" ; +LOCATE COMP "Dram_Clk" SITE "C17" ; +LOCATE COMP "Dram_Addr[1]" SITE "C10" ; +LOCATE COMP "Dram_Addr[2]" SITE "D8" ; +LOCATE COMP "Dram_Addr[4]" SITE "D13" ; +LOCATE COMP "Dram_Addr[5]" SITE "C13" ; +LOCATE COMP "Dram_Addr[6]" SITE "B13" ; +LOCATE COMP "Dram_Addr[7]" SITE "D15" ; +LOCATE COMP "Dram_Addr[8]" SITE "D14" ; +LOCATE COMP "Dram_Addr[9]" SITE "A14" ; +LOCATE COMP "Dram_Addr[11]" SITE "C16" ; +LOCATE COMP "Dram_Addr[12]" SITE "C14" ; +LOCATE COMP "Dram_Addr[10]" SITE "D9" ; +LOCATE COMP "Dram_DQMH" SITE "D16" ; +LOCATE COMP "Dram_DQML" SITE "A11" ; +LOCATE COMP "Dram_n_Cas" SITE "B11" ; +LOCATE COMP "Dram_n_Ras" SITE "C12" ; +LOCATE COMP "Dram_n_We" SITE "D12" ; +LOCATE COMP "Dram_n_cs" SITE "C11" ; +LOCATE COMP "Dram_Data[0]" SITE "A10" ; +LOCATE COMP "Dram_Data[1]" SITE "B9" ; +LOCATE COMP "Dram_Data[2]" SITE "B10" ; +LOCATE COMP "Dram_Data[3]" SITE "A9" ; +LOCATE COMP "Dram_Data[4]" SITE "B8" ; +LOCATE COMP "Dram_Data[5]" SITE "A8" ; +LOCATE COMP "Dram_Data[6]" SITE "C8" ; +LOCATE COMP "Dram_Data[7]" SITE "A7" ; +LOCATE COMP "Dram_Data[8]" SITE "A19" ; +LOCATE COMP "Dram_Data[9]" SITE "B18" ; +LOCATE COMP "Dram_Data[10]" SITE "A18" ; +LOCATE COMP "Dram_Data[11]" SITE "B17" ; +LOCATE COMP "Dram_Data[12]" SITE "A17" ; +LOCATE COMP "Dram_Data[13]" SITE "B15" ; +LOCATE COMP "Dram_Data[14]" SITE "B16" ; +LOCATE COMP "Dram_Data[15]" SITE "A16" ; +## SD/MMC PORT +IOBUF PORT "mmc_miso" IO_TYPE=LVCMOS25 PULLMODE=NONE ; +IOBUF PORT "mmc_dat1" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "mmc_dat2" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "mmc_n_cs" IO_TYPE=LVCMOS25 PULLMODE=NONE ; +IOBUF PORT "mmc_mosi" IO_TYPE=LVCMOS25 PULLMODE=NONE ; +IOBUF PORT "mmc_clk" IO_TYPE=LVCMOS25 ; +LOCATE COMP "mmc_miso" SITE "C2" ; +LOCATE COMP "mmc_clk" SITE "C3" ; +LOCATE COMP "mmc_mosi" SITE "B2" ; +LOCATE COMP "mmc_n_cs" SITE "B3" ; +## SYSCONFIG PARAMETERS +VCCIO_DERATE PERCENT 0; +SYSCONFIG CONFIG_IOVOLTAGE=3.3 SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=ENABLE SLAVE_PARALLEL_PORT=DISABLE BACKGROUND_RECONFIG=OFF TRANSFR=ON CONFIG_MODE=SPI_SERIAL DONE_OD=OFF DONE_EX=OFF MCCLK_FREQ=38.8 ; +## DIGITAL VIDEO OUT +IOBUF PORT "LVDS_Blue[0]" IO_TYPE=LVDS ; +IOBUF PORT "LVDS_Green[0]" IO_TYPE=LVDS ; +IOBUF PORT "LVDS_Red[0]" IO_TYPE=LVDS ; +IOBUF PORT "LVDS_ck[0]" IO_TYPE=LVDS ; +LOCATE COMP "LVDS_Red[0]" SITE "C1" ; +LOCATE COMP "LVDS_Blue[0]" SITE "A4" ; +LOCATE COMP "LVDS_Green[0]" SITE "A2" ; +LOCATE COMP "LVDS_ck[0]" SITE "G2" ; diff --git a/app/resources/boards/FleaFPGA-Ohm_(FT232H)/info.json b/app/resources/boards/FleaFPGA-Ohm_(FT232H)/info.json new file mode 100644 index 000000000..5bf59a793 --- /dev/null +++ b/app/resources/boards/FleaFPGA-Ohm_(FT232H)/info.json @@ -0,0 +1 @@ +{"label":"FleaFPGA-Ohm_(FT232H)","datasheet":"https://github.com/Basman74/FleaFPGA-Ohm","interface":"FTDI","arch":"ecp5","FPGAResources":{"ffs":24288,"luts":24288,"pios":96,"plbs":660,"brams":30}} \ No newline at end of file diff --git a/app/resources/boards/FleaFPGA-Ohm_(FT232H)/pinout.json b/app/resources/boards/FleaFPGA-Ohm_(FT232H)/pinout.json new file mode 100644 index 000000000..047308c52 --- /dev/null +++ b/app/resources/boards/FleaFPGA-Ohm_(FT232H)/pinout.json @@ -0,0 +1,110 @@ +[ +{"type":"input","name":"CLK","value":"H2"}, +{"type":"input","name":"Reset","value":"T17","pullmode":"UP"}, + +{"type":"output","name":"LED","value":"P2","pullmode":"NONE"}, + +{"type":"output","name":"slave_rx_i","value":"P1","pullmode":"NONE"}, +{"type":"input","name":"slave_tx_o","value":"P3"}, +{"type":"output","name":"slave_cts_i","value":"Y2","pullmode":"NONE"}, + +{"type":"input","name":"Button","value":"M13","pullmode":"NONE"}, + +{"type":"inout","name":"GPIO_IDSD","value":"N19","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_IDSC","value":"N20","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_2","value":"D17","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_3","value":"C18","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_4","value":"D19","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_5","value":"T20","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_6","value":"T19","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_7","value":"L19","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_8","value":"M20","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_9","value":"J19","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_10","value":"G19","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_11","value":"K19","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_12","value":"R18","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_13","value":"N16","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_14","value":"C20","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_15","value":"E17","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_16","value":"M17","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_17","value":"F17","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_18","value":"D18","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_19","value":"U18","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_20","value":"N17","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_21","value":"P16","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_22","value":"F19","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_23","value":"E20","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_24","value":"D20","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_25","value":"L20","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_26","value":"U17","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_27","value":"G18","pullmode":"NONE"}, + +{"type":"output","name":"sdram_clk","value":"C17","pullmode":"NONE"}, +{"type":"output","name":"sdram_cke","value":"C15","pullmode":"NONE"}, +{"type":"output","name":"sdram_wen","value":"D12","pullmode":"NONE"}, +{"type":"output","name":"sdram_rasn","value":"C12","pullmode":"NONE"}, +{"type":"output","name":"sdram_casn","value":"B11","pullmode":"NONE"}, +{"type":"output","name":"sdram_BA[0]","value":"A12","pullmode":"NONE"}, +{"type":"output","name":"sdram_BA[1]","value":"D11","pullmode":"NONE"}, +{"type":"output","name":"sdram_DQMH","value":"D16","pullmode":"NONE"}, +{"type":"output","name":"sdram_DQML","value":"A11","pullmode":"NONE"}, + +{"type":"output","name":"sdram_a0","value":"B12","pullmode":"NONE"}, +{"type":"output","name":"sdram_a1","value":"C10","pullmode":"NONE"}, +{"type":"output","name":"sdram_a2","value":"D8","pullmode":"NONE"}, +{"type":"output","name":"sdram_a3","value":"A13","pullmode":"NONE"}, +{"type":"output","name":"sdram_a4","value":"D13","pullmode":"NONE"}, +{"type":"output","name":"sdram_a5","value":"C13","pullmode":"NONE"}, +{"type":"output","name":"sdram_a6","value":"B13","pullmode":"NONE"}, +{"type":"output","name":"sdram_a7","value":"D15","pullmode":"NONE"}, +{"type":"output","name":"sdram_a8","value":"D14","pullmode":"NONE"}, +{"type":"output","name":"sdram_a9","value":"A14","pullmode":"NONE"}, +{"type":"output","name":"sdram_a10","value":"D9","pullmode":"NONE"}, +{"type":"output","name":"sdram_a11","value":"C16","pullmode":"NONE"}, +{"type":"output","name":"sdram_a12","value":"C14","pullmode":"NONE"}, + +{"type":"inout","name":"sdram_d0","value":"A10","pullmode":"NONE"}, +{"type":"inout","name":"sdram_d1","value":"B9","pullmode":"NONE"}, +{"type":"inout","name":"sdram_d2","value":"B10","pullmode":"NONE"}, +{"type":"inout","name":"sdram_d3","value":"A9","pullmode":"NONE"}, +{"type":"inout","name":"sdram_d4","value":"B8","pullmode":"NONE"}, +{"type":"inout","name":"sdram_d5","value":"A8","pullmode":"NONE"}, +{"type":"inout","name":"sdram_d6","value":"C8","pullmode":"NONE"}, +{"type":"inout","name":"sdram_d7","value":"A7","pullmode":"NONE"}, +{"type":"inout","name":"sdram_d8","value":"A19","pullmode":"NONE"}, +{"type":"inout","name":"sdram_d9","value":"B18","pullmode":"NONE"}, +{"type":"inout","name":"sdram_d10","value":"A18","pullmode":"NONE"}, +{"type":"inout","name":"sdram_d11","value":"B17","pullmode":"NONE"}, +{"type":"inout","name":"sdram_d12","value":"A17","pullmode":"NONE"}, +{"type":"inout","name":"sdram_d13","value":"B15","pullmode":"NONE"}, +{"type":"inout","name":"sdram_d14","value":"B16","pullmode":"NONE"}, +{"type":"inout","name":"sdram_d15","value":"A16","pullmode":"NONE"}, + +{"type":"output","name":"SD_Clk","value":"C3","pullmode":"NONE"}, +{"type":"output","name":"SD_n_CS","value":"B3","pullmode":"NONE"}, +{"type":"input","name":"SD_Miso","value":"C2","pullmode":"NONE"}, +{"type":"output","name":"SD_Mosi","value":"B2","pullmode":"NONE"}, +{"type":"inout","name":"SD_Dat1","value":"A3","pullmode":"NONE"}, +{"type":"inout","name":"SD_Dat2","value":"E1","pullmode":"NONE"}, + +{"type":"output","name":"SPI_Clk","value":"U3","pullmode":"NONE"}, +{"type":"output","name":"SPI_n_CS","value":"R2","pullmode":"NONE"}, +{"type":"input","name":"SPI_Miso","value":"V2","pullmode":"NONE"}, +{"type":"output","name":"SPI_Mosi","value":"W2","pullmode":"NONE"}, + +{"type":"inout","name":"PS2_clk1","value":"K2","pullmode":"UP"}, +{"type":"inout","name":"PS2_data1","value":"J1","pullmode":"UP"}, +{"type":"inout","name":"PS2_clk2","value":"N2","pullmode":"UP"}, +{"type":"inout","name":"PS2_data2","value":"M1","pullmode":"UP"}, +{"type":"input","name":"PS2_enable","value":"N1","pullmode":"UP"}, + +{"type":"output","name":"D2_Pos","value":"C1","pullmode":"NONE"}, +{"type":"output","name":"D2_Neg","value":"D1","pullmode":"NONE"}, +{"type":"output","name":"D1_Pos","value":"A2","pullmode":"NONE"}, +{"type":"output","name":"D1_Neg","value":"B1","pullmode":"NONE"}, +{"type":"output","name":"D0_Pos","value":"A4","pullmode":"NONE"}, +{"type":"output","name":"D0_Neg","value":"A5","pullmode":"NONE"}, +{"type":"output","name":"CK_Pos","value":"G2","pullmode":"NONE"}, +{"type":"output","name":"CK_Neg","value":"F1","pullmode":"NONE"} + +] \ No newline at end of file diff --git a/app/resources/boards/FleaFPGA-Ohm_(FT232H)/rules.json b/app/resources/boards/FleaFPGA-Ohm_(FT232H)/rules.json new file mode 100644 index 000000000..a066ec476 --- /dev/null +++ b/app/resources/boards/FleaFPGA-Ohm_(FT232H)/rules.json @@ -0,0 +1 @@ +{"input":[{"port":"clk","pin":"H2"}]} \ No newline at end of file diff --git a/app/resources/boards/FleaFPGA-Ohm_(USB-Blaster)/FleaFPGA_Ohm.pdf b/app/resources/boards/FleaFPGA-Ohm_(USB-Blaster)/FleaFPGA_Ohm.pdf new file mode 100644 index 000000000..5eac41b90 Binary files /dev/null and b/app/resources/boards/FleaFPGA-Ohm_(USB-Blaster)/FleaFPGA_Ohm.pdf differ diff --git a/app/resources/boards/FleaFPGA-Ohm_(USB-Blaster)/JTAG_connector.png b/app/resources/boards/FleaFPGA-Ohm_(USB-Blaster)/JTAG_connector.png new file mode 100644 index 000000000..29b8174cf Binary files /dev/null and b/app/resources/boards/FleaFPGA-Ohm_(USB-Blaster)/JTAG_connector.png differ diff --git a/app/resources/boards/FleaFPGA-Ohm_(USB-Blaster)/___pinout.lpf b/app/resources/boards/FleaFPGA-Ohm_(USB-Blaster)/___pinout.lpf new file mode 100644 index 000000000..b67b94e65 --- /dev/null +++ b/app/resources/boards/FleaFPGA-Ohm_(USB-Blaster)/___pinout.lpf @@ -0,0 +1,456 @@ +BLOCK RESETPATHS; +BLOCK ASYNCPATHS; +## ColorLight-5A-75B v2.0 and v2.1 + +# The clock "usb" and "gpdi" sheet +LOCATE COMP "clk_25mhz" SITE "P6"; +IOBUF PORT "clk_25mhz" PULLMODE=NONE IO_TYPE=LVCMOS33; +FREQUENCY PORT "clk_25mhz" 25 MHZ; + +# JTAG and SPI FLASH voltage 3.3V and options to boot from SPI flash +# write to FLASH possible any time from JTAG: +#SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 MASTER_SPI_PORT=ENABLE SLAVE_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE; +# write to FLASH possible from user bitstream: +# SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 MASTER_SPI_PORT=DISABLE SLAVE_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE; + +## USBSERIAL FTDI-FPGA serial port "usb" sheet +#LOCATE COMP "ftdi_rxd" SITE "L4"; # FPGA transmits to ftdi +#LOCATE COMP "ftdi_txd" SITE "M1"; # FPGA receives from ftdi +#LOCATE COMP "ftdi_nrts" SITE "M3"; # FPGA receives +#LOCATE COMP "ftdi_ndtr" SITE "N1"; # FPGA receives +#LOCATE COMP "ftdi_txden" SITE "L3"; # FPGA receives +#IOBUF PORT "ftdi_rxd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "ftdi_txd" PULLMODE=UP IO_TYPE=LVCMOS33; +#IOBUF PORT "ftdi_nrts" PULLMODE=UP IO_TYPE=LVCMOS33; +#IOBUF PORT "ftdi_ndtr" PULLMODE=UP IO_TYPE=LVCMOS33; +#IOBUF PORT "ftdi_txden" PULLMODE=UP IO_TYPE=LVCMOS33; + +## LED indicators "blinkey" and "gpio" sheet +#LOCATE COMP "led[7]" SITE "H3"; +#LOCATE COMP "led[6]" SITE "E1"; +#LOCATE COMP "led[5]" SITE "E2"; +#LOCATE COMP "led[4]" SITE "D1"; +#LOCATE COMP "led[3]" SITE "D2"; +#LOCATE COMP "led[2]" SITE "C1"; +#LOCATE COMP "led[1]" SITE "C2"; +#LOCATE COMP "led[0]" SITE "B2"; +#IOBUF PORT "led[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "led[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "led[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "led[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "led[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "led[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "led[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "led[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +## Pushbuttons "blinkey", "flash", "power", "gpdi" sheet +#LOCATE COMP "btn[0]" SITE "D6"; # BTN_PWRn (inverted logic) +#LOCATE COMP "btn[1]" SITE "R1"; # FIRE1 +#LOCATE COMP "btn[2]" SITE "T1"; # FIRE2 +#LOCATE COMP "btn[3]" SITE "R18"; # UP W1->R18 +#LOCATE COMP "btn[4]" SITE "V1"; # DOWN +#LOCATE COMP "btn[5]" SITE "U1"; # LEFT +#LOCATE COMP "btn[6]" SITE "H16"; # RIGHT Y2->H16 +#IOBUF PORT "btn[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "btn[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "btn[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "btn[3]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "btn[4]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "btn[5]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "btn[6]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; + +## DIP switch "blinkey", "gpio" sheet +#LOCATE COMP "sw[0]" SITE "E8"; # SW1 +#LOCATE COMP "sw[1]" SITE "D8"; # SW2 +#LOCATE COMP "sw[2]" SITE "D7"; # SW3 +#LOCATE COMP "sw[3]" SITE "E7"; # SW4 +#IOBUF PORT "sw[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "sw[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "sw[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "sw[3]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; + +## SPI OLED DISPLAY SSD1331 (Color) or SSD1306 (B/W) "blinkey", "usb" sheet +#LOCATE COMP "oled_clk" SITE "P4"; +#LOCATE COMP "oled_mosi" SITE "P3"; +#LOCATE COMP "oled_dc" SITE "P1"; +#LOCATE COMP "oled_resn" SITE "P2"; +#LOCATE COMP "oled_csn" SITE "N2"; +#IOBUF PORT "oled_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "oled_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "oled_dc" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "oled_resn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "oled_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## SPI Flash chip "flash" sheet +LOCATE COMP "flash_csn" SITE "R2"; +LOCATE COMP "flash_clk" SITE "U3"; +LOCATE COMP "flash_mosi" SITE "W2"; +LOCATE COMP "flash_miso" SITE "V2"; +LOCATE COMP "flash_holdn" SITE "W1"; +LOCATE COMP "flash_wpn" SITE "Y2"; +#LOCATE COMP "flash_csspin" SITE "AJ3"; +#LOCATE COMP "flash_initn" SITE "AG4"; +#LOCATE COMP "flash_done" SITE "AJ4"; +#LOCATE COMP "flash_programn" SITE "AH4"; +#LOCATE COMP "flash_cfg_select[0]" SITE "AM4"; +#LOCATE COMP "flash_cfg_select[1]" SITE "AL4"; +#LOCATE COMP "flash_cfg_select[2]" SITE "AK4"; +IOBUF PORT "flash_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_clk" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_miso" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_holdn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_wpn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_csspin" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_initn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_done" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_programn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_cfg_select[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_cfg_select[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_cfg_select[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; + +## SD card "sdcard", "usb" sheet +#LOCATE COMP "sd_clk" SITE "H2"; # sd_clk WiFi_GPIO14 +#LOCATE COMP "sd_cmd" SITE "J1"; # sd_cmd_di (MOSI) WiFi GPIO15 +#LOCATE COMP "sd_d[0]" SITE "J3"; # sd_dat0_do (MISO) WiFi GPIO2 +#LOCATE COMP "sd_d[1]" SITE "H1"; # sd_dat1_irq WiFi GPIO4 +#LOCATE COMP "sd_d[2]" SITE "K1"; # sd_dat2 WiFi_GPIO12 +#LOCATE COMP "sd_d[3]" SITE "K2"; # sd_dat3_csn WiFi_GPIO13 +#LOCATE COMP "sd_wp" SITE "P5"; # not connected +#LOCATE COMP "sd_cdn" SITE "N5"; # not connected +#IOBUF PORT "sd_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "sd_cmd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "sd_d[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "sd_d[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "sd_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; # WiFi GPIO12 pulldown bootstrapping requirement +#IOBUF PORT "sd_d[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "sd_wp" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "sd_cdn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## ADC SPI (MAX11123) "analog", "ram" sheet +#LOCATE COMP "adc_csn" SITE "R17"; +#LOCATE COMP "adc_mosi" SITE "R16"; +#LOCATE COMP "adc_miso" SITE "U16"; +#LOCATE COMP "adc_sclk" SITE "P17"; +#IOBUF PORT "adc_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "adc_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "adc_miso" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "adc_sclk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## Audio 4-bit DAC "analog", "gpio" sheet +# 4-bit mode can drive down to 75 ohm load impedance. +# Lower impedance leads to IO overload, +# FPGA will stop working and need reboot. +# For standard 17 ohm earphones on PCB v1.7: +# use bits 2,3 as input (High-Z) and drive only bits 0,1. +# PCB v2.1.2 can use full 4 bits and 16mA drive for 17 ohm earphones. +#LOCATE COMP "audio_l[3]" SITE "B3"; # JACK TIP (left audio) +#LOCATE COMP "audio_l[2]" SITE "C3"; +#LOCATE COMP "audio_l[1]" SITE "D3"; +#LOCATE COMP "audio_l[0]" SITE "E4"; +#LOCATE COMP "audio_r[3]" SITE "C5"; # JACK RING1 (right audio) +#LOCATE COMP "audio_r[2]" SITE "D5"; +#LOCATE COMP "audio_r[1]" SITE "B5"; +#LOCATE COMP "audio_r[0]" SITE "A3"; +#LOCATE COMP "audio_v[3]" SITE "E5"; # JACK RING2 (video or digital audio) +#LOCATE COMP "audio_v[2]" SITE "F5"; +#LOCATE COMP "audio_v[1]" SITE "F2"; +#LOCATE COMP "audio_v[0]" SITE "H5"; +#IOBUF PORT "audio_l[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +#IOBUF PORT "audio_l[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +#IOBUF PORT "audio_l[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +#IOBUF PORT "audio_l[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +#IOBUF PORT "audio_r[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +#IOBUF PORT "audio_r[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +#IOBUF PORT "audio_r[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +#IOBUF PORT "audio_r[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +#IOBUF PORT "audio_v[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +#IOBUF PORT "audio_v[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +#IOBUF PORT "audio_v[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +#IOBUF PORT "audio_v[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; + +## WiFi ESP-32 "wifi", "usb", "flash" sheet +# other pins are shared with GP/GN, SD card and JTAG +#LOCATE COMP "wifi_en" SITE "F1"; # enable/reset WiFi +#LOCATE COMP "wifi_rxd" SITE "K3"; # FPGA transmits to WiFi +#LOCATE COMP "wifi_txd" SITE "K4"; # FPGA receives from WiFi +#LOCATE COMP "wifi_gpio0" SITE "L2"; +#LOCATE COMP "wifi_gpio5" SITE "N4"; # WIFI LED +#LOCATE COMP "wifi_gpio16" SITE "L1"; # Serial1 RX +#LOCATE COMP "wifi_gpio17" SITE "N3"; # Serial1 TX +# LOCATE COMP "prog_done" SITE "Y3"; # not GPIO, always active +#IOBUF PORT "wifi_en" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "wifi_rxd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "wifi_txd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "wifi_gpio0" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "wifi_gpio16" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "wifi_gpio17" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +# IOBUF PORT "prog_done" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## PCB antenna 433 MHz (may be also used for FM) "usb" sheet +#LOCATE COMP "ant_433mhz" SITE "G1"; +#IOBUF PORT "ant_433mhz" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +## Second USB port "US2" going directly into FPGA "usb", "ram" sheet +#LOCATE COMP "usb_fpga_dp" SITE "E16"; # single ended or differential input only +#LOCATE COMP "usb_fpga_dn" SITE "F16"; +#IOBUF PORT "usb_fpga_dp" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +#IOBUF PORT "usb_fpga_dn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +#LOCATE COMP "usb_fpga_bd_dp" SITE "D15"; # differential bidirectional +#LOCATE COMP "usb_fpga_bd_dn" SITE "E15"; +#IOBUF PORT "usb_fpga_bd_dp" PULLMODE=NONE IO_TYPE=LVCMOS33D DRIVE=4; +#IOBUF PORT "usb_fpga_bd_dn" PULLMODE=NONE IO_TYPE=LVCMOS33D DRIVE=4; +#LOCATE COMP "usb_fpga_pu_dp" SITE "B12"; # pull up/down control +#LOCATE COMP "usb_fpga_pu_dn" SITE "C12"; +#IOBUF PORT "usb_fpga_pu_dp" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +#IOBUF PORT "usb_fpga_pu_dn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; + +## JTAG ESP-32 "usb" sheet +# connected to FT231X and ESP-32 +# commented out because those are dedicated pins, not directly useable as GPIO +# but could be used by some vendor-specific JTAG bridging (boundary scan) module +#LOCATE COMP "jtag_tdi" SITE "R5"; # FTDI_nRI FPGA receives +#LOCATE COMP "jtag_tdo" SITE "V4"; # FTDI_nCTS FPGA transmits +#LOCATE COMP "jtag_tck" SITE "T5"; # FTDI_nDSR FPGA receives +#LOCATE COMP "jtag_tms" SITE "U5"; # FTDI_nDCD FPGA receives +#IOBUF PORT "jtag_tdi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "jtag_tdo" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "jtag_tck" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "jtag_tms" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## SDRAM "ram" sheet +LOCATE COMP "sdram_clk" SITE "F19"; +LOCATE COMP "sdram_cke" SITE "F20"; +LOCATE COMP "sdram_csn" SITE "P20"; +LOCATE COMP "sdram_wen" SITE "T20"; +LOCATE COMP "sdram_rasn" SITE "R20"; +LOCATE COMP "sdram_casn" SITE "T19"; +LOCATE COMP "sdram_a[0]" SITE "M20"; +LOCATE COMP "sdram_a[1]" SITE "M19"; +LOCATE COMP "sdram_a[2]" SITE "L20"; +LOCATE COMP "sdram_a[3]" SITE "L19"; +LOCATE COMP "sdram_a[4]" SITE "K20"; +LOCATE COMP "sdram_a[5]" SITE "K19"; +LOCATE COMP "sdram_a[6]" SITE "K18"; +LOCATE COMP "sdram_a[7]" SITE "J20"; +LOCATE COMP "sdram_a[8]" SITE "J19"; +LOCATE COMP "sdram_a[9]" SITE "H20"; +LOCATE COMP "sdram_a[10]" SITE "N19"; +LOCATE COMP "sdram_a[11]" SITE "G20"; +LOCATE COMP "sdram_a[12]" SITE "G19"; +LOCATE COMP "sdram_ba[0]" SITE "P19"; +LOCATE COMP "sdram_ba[1]" SITE "N20"; +LOCATE COMP "sdram_dqm[0]" SITE "U19"; +LOCATE COMP "sdram_dqm[1]" SITE "E20"; +LOCATE COMP "sdram_d[0]" SITE "J16"; +LOCATE COMP "sdram_d[1]" SITE "L18"; +LOCATE COMP "sdram_d[2]" SITE "M18"; +LOCATE COMP "sdram_d[3]" SITE "N18"; +LOCATE COMP "sdram_d[4]" SITE "P18"; +LOCATE COMP "sdram_d[5]" SITE "T18"; +LOCATE COMP "sdram_d[6]" SITE "T17"; +LOCATE COMP "sdram_d[7]" SITE "U20"; +LOCATE COMP "sdram_d[8]" SITE "E19"; +LOCATE COMP "sdram_d[9]" SITE "D20"; +LOCATE COMP "sdram_d[10]" SITE "D19"; +LOCATE COMP "sdram_d[11]" SITE "C20"; +LOCATE COMP "sdram_d[12]" SITE "E18"; +LOCATE COMP "sdram_d[13]" SITE "F18"; +LOCATE COMP "sdram_d[14]" SITE "J18"; +LOCATE COMP "sdram_d[15]" SITE "J17"; +IOBUF PORT "sdram_clk" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_cke" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_csn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_wen" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_rasn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_casn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_ba[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_ba[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_dqm[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_dqm[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[13]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[14]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[15]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +# GPDI differential interface (Video) "gpdi" sheet +#LOCATE COMP "gpdi_dp[0]" SITE "A16"; # Blue + +#LOCATE COMP "gpdi_dn[0]" SITE "B16"; # Blue - +#LOCATE COMP "gpdi_dp[1]" SITE "A14"; # Green + +#LOCATE COMP "gpdi_dn[1]" SITE "C14"; # Green - +#LOCATE COMP "gpdi_dp[2]" SITE "A12"; # Red + +#LOCATE COMP "gpdi_dn[2]" SITE "A13"; # Red - +#LOCATE COMP "gpdi_dp[3]" SITE "A17"; # Clock + +#LOCATE COMP "gpdi_dn[3]" SITE "B18"; # Clock - +#LOCATE COMP "gpdi_ethp" SITE "A19"; # Ethernet + +#LOCATE COMP "gpdi_ethn" SITE "B20"; # Ethernet - +#LOCATE COMP "gpdi_cec" SITE "A18"; +#LOCATE COMP "gpdi_sda" SITE "B19"; # I2C shared with RTC +#LOCATE COMP "gpdi_scl" SITE "E12"; # I2C shared with RTC C12->E12 +#IOBUF PORT "gpdi_dp[0]" IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "gpdi_dn[0]" IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "gpdi_dp[1]" IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "gpdi_dn[1]" IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "gpdi_dp[2]" IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "gpdi_dn[2]" IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "gpdi_dp[3]" IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "gpdi_dn[3]" IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "gpdi_ethp" IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "gpdi_ethn" IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "gpdi_cec" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "gpdi_sda" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "gpdi_scl" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +# GPIO (default single-ended) "gpio", "ram", "gpdi" sheet +# Pins enumerated gp[0-27], gn[0-27]. +# With differential mode enabled on Lattice, +# gp[] (+) are used, gn[] (-) are ignored from design +# as they handle inverted signal by default. +# To enable differential, rename LVCMOS33->LVCMOS33D +LOCATE COMP "gp[0]" SITE "B11"; # J1_5+ GP0 +LOCATE COMP "gn[0]" SITE "C11"; # J1_5- GN0 +LOCATE COMP "gp[1]" SITE "A10"; # J1_7+ GP1 +LOCATE COMP "gn[1]" SITE "A11"; # J1_7- GN1 +LOCATE COMP "gp[2]" SITE "A9"; # J1_9+ GP2 +LOCATE COMP "gn[2]" SITE "B10"; # J1_9- GN2 +LOCATE COMP "gp[3]" SITE "B9"; # J1_11+ GP3 +LOCATE COMP "gn[3]" SITE "C10"; # J1_11- GN3 +LOCATE COMP "gp[4]" SITE "A7"; # J1_13+ GP4 +LOCATE COMP "gn[4]" SITE "A8"; # J1_13- GN4 +LOCATE COMP "gp[5]" SITE "C8"; # J1_15+ GP5 +LOCATE COMP "gn[5]" SITE "B8"; # J1_15- GN5 +LOCATE COMP "gp[6]" SITE "C6"; # J1_17+ GP6 +LOCATE COMP "gn[6]" SITE "C7"; # J1_17- GN6 +IOBUF PORT "gp[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +LOCATE COMP "gp[7]" SITE "A6"; # J1_23+ GP7 +LOCATE COMP "gn[7]" SITE "B6"; # J1_23- GN7 +LOCATE COMP "gp[8]" SITE "A4"; # J1_25+ GP8 +LOCATE COMP "gn[8]" SITE "A5"; # J1_25- GN8 +LOCATE COMP "gp[9]" SITE "A2"; # J1_27+ GP9 +LOCATE COMP "gn[9]" SITE "B1"; # J1_27- GN9 +LOCATE COMP "gp[10]" SITE "C4"; # J1_29+ GP10 WIFI_GPIO27 +LOCATE COMP "gn[10]" SITE "B4"; # J1_29- GN10 +LOCATE COMP "gp[11]" SITE "F4"; # J1_31+ GP11 WIFI_GPIO25 +LOCATE COMP "gn[11]" SITE "E3"; # J1_31- GN11 WIFI_GPIO26 +LOCATE COMP "gp[12]" SITE "G3"; # J1_33+ GP12 WIFI_GPIO32 +LOCATE COMP "gn[12]" SITE "F3"; # J1_33- GN12 WIFI_GPIO33 +LOCATE COMP "gp[13]" SITE "H4"; # J1_35+ GP13 WIFI_GPIO34 +LOCATE COMP "gn[13]" SITE "G5"; # J1_35- GN13 WIFI_GPIO35 +IOBUF PORT "gp[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[8]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[8]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[9]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[9]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[10]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[10]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[11]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[11]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[12]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[12]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[13]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[13]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +LOCATE COMP "gp[14]" SITE "U18"; # J2_5+ GP14 +LOCATE COMP "gn[14]" SITE "U17"; # J2_5- GN14 +LOCATE COMP "gp[15]" SITE "N17"; # J2_7+ GP15 +LOCATE COMP "gn[15]" SITE "P16"; # J2_7- GN15 +LOCATE COMP "gp[16]" SITE "N16"; # J2_9+ GP16 +LOCATE COMP "gn[16]" SITE "M17"; # J2_9- GN16 +LOCATE COMP "gp[17]" SITE "L16"; # J2_11+ GP17 +LOCATE COMP "gn[17]" SITE "L17"; # J2_11- GN17 +LOCATE COMP "gp[18]" SITE "H18"; # J2_13+ GP18 +LOCATE COMP "gn[18]" SITE "H17"; # J2_13- GN18 +LOCATE COMP "gp[19]" SITE "F17"; # J2_15+ GP19 +LOCATE COMP "gn[19]" SITE "G18"; # J2_15- GN19 +LOCATE COMP "gp[20]" SITE "D18"; # J2_17+ GP20 +LOCATE COMP "gn[20]" SITE "E17"; # J2_17- GN20 +IOBUF PORT "gp[14]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[14]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[15]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[15]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[16]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[16]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[17]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[17]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[18]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[18]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[19]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[19]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +LOCATE COMP "gp[21]" SITE "C18"; # J2_23+ GP21 +LOCATE COMP "gn[21]" SITE "D17"; # J2_23- GN21 +LOCATE COMP "gp[22]" SITE "B15"; # J2_25+ GP22 D15->B15 +LOCATE COMP "gn[22]" SITE "C15"; # J2_25- GN22 E15->C15 +LOCATE COMP "gp[23]" SITE "B17"; # J2_27+ GP23 +LOCATE COMP "gn[23]" SITE "C17"; # J2_27- GN23 +LOCATE COMP "gp[24]" SITE "C16"; # J2_29+ GP24 +LOCATE COMP "gn[24]" SITE "D16"; # J2_29- GN24 +LOCATE COMP "gp[25]" SITE "D14"; # J2_31+ GP25 B15->D14 +LOCATE COMP "gn[25]" SITE "E14"; # J2_31- GN25 C15->E14 +LOCATE COMP "gp[26]" SITE "B13"; # J2_33+ GP26 +LOCATE COMP "gn[26]" SITE "C13"; # J2_33- GN26 +LOCATE COMP "gp[27]" SITE "D13"; # J2_35+ GP27 +LOCATE COMP "gn[27]" SITE "E13"; # J2_35- GN27 +IOBUF PORT "gp[21]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[21]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[22]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[22]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[23]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[23]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[24]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[24]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[25]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[25]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[26]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[26]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[27]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[27]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## PROGRAMN (reload bitstream from FLASH, exit from bootloader) +# PCB v2.0.5 and higher +LOCATE COMP "user_programn" SITE "M4"; +IOBUF PORT "user_programn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## SHUTDOWN "power", "ram" sheet (connected from PCB v1.7.5) +# on PCB v1.7 shutdown is not connected to FPGA +LOCATE COMP "shutdown" SITE "G16"; # FPGA receives +IOBUF PORT "shutdown" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; diff --git a/app/resources/boards/FleaFPGA-Ohm_(USB-Blaster)/info.json b/app/resources/boards/FleaFPGA-Ohm_(USB-Blaster)/info.json new file mode 100644 index 000000000..f54042793 --- /dev/null +++ b/app/resources/boards/FleaFPGA-Ohm_(USB-Blaster)/info.json @@ -0,0 +1,13 @@ +{ + "label": "FleaFPGA_Ohm_(USB-Blaster)", + "datasheet": "https://github.com/Basman74/FleaFPGA-Ohm", + "interface": "FTDI", + "arch": "ecp5", + "FPGAResources": { + "ffs": 24288, + "luts": 24288, + "pios": 96, + "plbs": 660, + "brams": 30 + } +} \ No newline at end of file diff --git a/app/resources/boards/FleaFPGA-Ohm_(USB-Blaster)/pinout.json b/app/resources/boards/FleaFPGA-Ohm_(USB-Blaster)/pinout.json new file mode 100644 index 000000000..047308c52 --- /dev/null +++ b/app/resources/boards/FleaFPGA-Ohm_(USB-Blaster)/pinout.json @@ -0,0 +1,110 @@ +[ +{"type":"input","name":"CLK","value":"H2"}, +{"type":"input","name":"Reset","value":"T17","pullmode":"UP"}, + +{"type":"output","name":"LED","value":"P2","pullmode":"NONE"}, + +{"type":"output","name":"slave_rx_i","value":"P1","pullmode":"NONE"}, +{"type":"input","name":"slave_tx_o","value":"P3"}, +{"type":"output","name":"slave_cts_i","value":"Y2","pullmode":"NONE"}, + +{"type":"input","name":"Button","value":"M13","pullmode":"NONE"}, + +{"type":"inout","name":"GPIO_IDSD","value":"N19","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_IDSC","value":"N20","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_2","value":"D17","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_3","value":"C18","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_4","value":"D19","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_5","value":"T20","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_6","value":"T19","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_7","value":"L19","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_8","value":"M20","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_9","value":"J19","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_10","value":"G19","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_11","value":"K19","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_12","value":"R18","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_13","value":"N16","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_14","value":"C20","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_15","value":"E17","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_16","value":"M17","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_17","value":"F17","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_18","value":"D18","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_19","value":"U18","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_20","value":"N17","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_21","value":"P16","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_22","value":"F19","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_23","value":"E20","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_24","value":"D20","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_25","value":"L20","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_26","value":"U17","pullmode":"NONE"}, +{"type":"inout","name":"GPIO_27","value":"G18","pullmode":"NONE"}, + +{"type":"output","name":"sdram_clk","value":"C17","pullmode":"NONE"}, +{"type":"output","name":"sdram_cke","value":"C15","pullmode":"NONE"}, +{"type":"output","name":"sdram_wen","value":"D12","pullmode":"NONE"}, +{"type":"output","name":"sdram_rasn","value":"C12","pullmode":"NONE"}, +{"type":"output","name":"sdram_casn","value":"B11","pullmode":"NONE"}, +{"type":"output","name":"sdram_BA[0]","value":"A12","pullmode":"NONE"}, +{"type":"output","name":"sdram_BA[1]","value":"D11","pullmode":"NONE"}, +{"type":"output","name":"sdram_DQMH","value":"D16","pullmode":"NONE"}, +{"type":"output","name":"sdram_DQML","value":"A11","pullmode":"NONE"}, + +{"type":"output","name":"sdram_a0","value":"B12","pullmode":"NONE"}, +{"type":"output","name":"sdram_a1","value":"C10","pullmode":"NONE"}, +{"type":"output","name":"sdram_a2","value":"D8","pullmode":"NONE"}, +{"type":"output","name":"sdram_a3","value":"A13","pullmode":"NONE"}, +{"type":"output","name":"sdram_a4","value":"D13","pullmode":"NONE"}, +{"type":"output","name":"sdram_a5","value":"C13","pullmode":"NONE"}, +{"type":"output","name":"sdram_a6","value":"B13","pullmode":"NONE"}, +{"type":"output","name":"sdram_a7","value":"D15","pullmode":"NONE"}, +{"type":"output","name":"sdram_a8","value":"D14","pullmode":"NONE"}, +{"type":"output","name":"sdram_a9","value":"A14","pullmode":"NONE"}, +{"type":"output","name":"sdram_a10","value":"D9","pullmode":"NONE"}, +{"type":"output","name":"sdram_a11","value":"C16","pullmode":"NONE"}, +{"type":"output","name":"sdram_a12","value":"C14","pullmode":"NONE"}, + +{"type":"inout","name":"sdram_d0","value":"A10","pullmode":"NONE"}, +{"type":"inout","name":"sdram_d1","value":"B9","pullmode":"NONE"}, +{"type":"inout","name":"sdram_d2","value":"B10","pullmode":"NONE"}, +{"type":"inout","name":"sdram_d3","value":"A9","pullmode":"NONE"}, +{"type":"inout","name":"sdram_d4","value":"B8","pullmode":"NONE"}, +{"type":"inout","name":"sdram_d5","value":"A8","pullmode":"NONE"}, +{"type":"inout","name":"sdram_d6","value":"C8","pullmode":"NONE"}, +{"type":"inout","name":"sdram_d7","value":"A7","pullmode":"NONE"}, +{"type":"inout","name":"sdram_d8","value":"A19","pullmode":"NONE"}, +{"type":"inout","name":"sdram_d9","value":"B18","pullmode":"NONE"}, +{"type":"inout","name":"sdram_d10","value":"A18","pullmode":"NONE"}, +{"type":"inout","name":"sdram_d11","value":"B17","pullmode":"NONE"}, +{"type":"inout","name":"sdram_d12","value":"A17","pullmode":"NONE"}, +{"type":"inout","name":"sdram_d13","value":"B15","pullmode":"NONE"}, +{"type":"inout","name":"sdram_d14","value":"B16","pullmode":"NONE"}, +{"type":"inout","name":"sdram_d15","value":"A16","pullmode":"NONE"}, + +{"type":"output","name":"SD_Clk","value":"C3","pullmode":"NONE"}, +{"type":"output","name":"SD_n_CS","value":"B3","pullmode":"NONE"}, +{"type":"input","name":"SD_Miso","value":"C2","pullmode":"NONE"}, +{"type":"output","name":"SD_Mosi","value":"B2","pullmode":"NONE"}, +{"type":"inout","name":"SD_Dat1","value":"A3","pullmode":"NONE"}, +{"type":"inout","name":"SD_Dat2","value":"E1","pullmode":"NONE"}, + +{"type":"output","name":"SPI_Clk","value":"U3","pullmode":"NONE"}, +{"type":"output","name":"SPI_n_CS","value":"R2","pullmode":"NONE"}, +{"type":"input","name":"SPI_Miso","value":"V2","pullmode":"NONE"}, +{"type":"output","name":"SPI_Mosi","value":"W2","pullmode":"NONE"}, + +{"type":"inout","name":"PS2_clk1","value":"K2","pullmode":"UP"}, +{"type":"inout","name":"PS2_data1","value":"J1","pullmode":"UP"}, +{"type":"inout","name":"PS2_clk2","value":"N2","pullmode":"UP"}, +{"type":"inout","name":"PS2_data2","value":"M1","pullmode":"UP"}, +{"type":"input","name":"PS2_enable","value":"N1","pullmode":"UP"}, + +{"type":"output","name":"D2_Pos","value":"C1","pullmode":"NONE"}, +{"type":"output","name":"D2_Neg","value":"D1","pullmode":"NONE"}, +{"type":"output","name":"D1_Pos","value":"A2","pullmode":"NONE"}, +{"type":"output","name":"D1_Neg","value":"B1","pullmode":"NONE"}, +{"type":"output","name":"D0_Pos","value":"A4","pullmode":"NONE"}, +{"type":"output","name":"D0_Neg","value":"A5","pullmode":"NONE"}, +{"type":"output","name":"CK_Pos","value":"G2","pullmode":"NONE"}, +{"type":"output","name":"CK_Neg","value":"F1","pullmode":"NONE"} + +] \ No newline at end of file diff --git a/app/resources/boards/FleaFPGA-Ohm_(USB-Blaster)/rules.json b/app/resources/boards/FleaFPGA-Ohm_(USB-Blaster)/rules.json new file mode 100644 index 000000000..537c95007 --- /dev/null +++ b/app/resources/boards/FleaFPGA-Ohm_(USB-Blaster)/rules.json @@ -0,0 +1 @@ +{"input":[{"port":"CLK","pin":"H2"}]} \ No newline at end of file diff --git a/app/resources/boards/menu.json b/app/resources/boards/menu.json index f1fd27976..69608a69c 100644 --- a/app/resources/boards/menu.json +++ b/app/resources/boards/menu.json @@ -65,7 +65,10 @@ "ColorLight-i5-v7.0_(USB-Blaster)", "iCESugar-Pro_(FT2232H)", "iCESugar-Pro_(FT232H)", - "iCESugar-Pro_(USB-Blaster)" + "iCESugar-Pro_(USB-Blaster)", + "FleaFPGA-Ohm_(FT2232H)", + "FleaFPGA-Ohm_(FT232H)", + "FleaFPGA-Ohm_(USB-Blaster)" ] } ]