Verify throws error when using EHXPLLL or other modules - build works, and it works on HW

[goran-mahovlic]

Hi to all, thanks again on this amazing tool, I am still learning how to use it, but now I have some useful samples for workshop.

But I have tried to get pll as block, and now I am in trouble.

And got error: Unknown module type: EHXPLLL

I am trying to add GPDI output, and I created all needed blocks except PLL

[goran-mahovlic]

It looks like I can build and upload sample, and that only problem could be in verify.

Yes, problem is in verify, build works, and sample also works on HW

I will do more cleanup after workshop, but initial samples are here: https://github.com/intergalaktik/icestudio-examples/tree/master/ulx3s

[cavearr]

Hi Goran! thanks for your feedback! i'm trying your examples and looking for the problem.

Thanks a lot!

[goran-mahovlic]

Thanks!

This is latest sample where everything works when build and upload, but verify fails...

https://github.com/intergalaktik/icestudio-examples/blob/master/ulx3s/fpga-odysseus/8._GPDI_Tricolore.ice

I will need to change picture of monitor - for now I just reuse yours.

[cavearr]

I am researching the problem and found the error but I am thinking how to fix it (at least it is one step).

The problem lies in a verilog statement that I think iverilog supports us, or at least not with the default Apio flags.

I'm working on it, I'll tell you ASAP!

[cavearr]

what Icestudio version are you using?

[goran-mahovlic]

what Icestudio version are you using?

I am actually copy pasting samples from @mmicko apio workshop so maybe we could grab flags from there

https://github.com/ulx3s/fpga-odysseus

[SiccoDwars]

I hadthe same issue: verify fails, build works.
Code as .ice file attached.
Icestudio version 0.7.1w202110170310
Below my 'Command output'.
But just when writing this post I looked once again and spotted that I had a leftover comma in an instantiation. After removing that "," on my line 105 in the Icestudio code block, the Verify no longer complains. But why then did the Build never complain???

  __set APIO_HOME_DIR="C:\Users\HP\.icestudio\apio"& "C:\Users\HP\.icestudio\venv\Scripts\apio.exe" verify --board iCEBreaker -p "C:\Users\HP\OneDrive\Documents\icestudio\ice-build\SBSPI Hardware SPI 2048x16"_

(DEBUG) Profile path: C:\Users\HP\.icestudio\apio\profile.json
(DEBUG) Home_dir: C:\Users\HP\.icestudio\apio

---> WARNING: no PCF file found (.pcf)

iverilog -o hardware.out -D VCD_OUTPUT= C:\Users\HP\.icestudio\apio\packages\toolchain-yosys\share\yosys/ice40/cells_sim.v main.v
main.v:367: syntax error
main.v:326: error: Syntax error in instance port expression(s).
scons: *** [hardware.out] Error 2
========================= [ ERROR ] Took 0.72 seconds =========================_

SBSPI Hardware SPI 2048x16_verify_fails_build_works.zip

[stas2k]

I have the same issue when using EHXPLLL in an ECP5 design. Build works, but Verify does not. Running version 0.9.2

iverilog -B "/home/stas/.icestudio/apio/packages/tools-oss-cad-suite/lib/ivl" -o hardware.out -D VCD_OUTPUT= -D NO_INCLUDES "/home/stas/.icestudio/apio/packages/tools-oss-cad-suite/share/yosys/ecp5/cells_sim.v" PxsCourt.v PxsStrVGAJoin.v PxsVGAComp.v VGASyncGen.v main.v
VGASyncGen.v:62: error: Unknown module type: EHXPLLL
2 error(s) during elaboration.
*** These modules were missing:
EHXPLLL referenced 1 times.
***
scons: *** [hardware.out] Error 2
========================= [ ERROR ] Took 0.08 seconds =========================

[cavearr]

with a lot of delay but @TeaOfJay fix it, the pr is merged into apio develop branch. thanks aganin, i'm closing this thread, but if the error appears reopen it.

Thanks @TeaOfJay !