diff --git a/apio/resources/distribution.json b/apio/resources/distribution.json
index 6da0c95b..74b69d6c 100644
--- a/apio/resources/distribution.json
+++ b/apio/resources/distribution.json
@@ -4,7 +4,7 @@
     "drivers": ">=1.1.0",
     "examples": ">=0.0.7",
     "graphviz": ">=12.1.2",
-    "oss-cad-suite": ">=0.2.0"
+    "oss-cad-suite": ">=0.2.1"
   },
   "pip_packages": {
     "blackiceprog": ">=2.0.0,<3.0.0",
diff --git a/apio/resources/packages.json b/apio/resources/packages.json
index 7c25552d..376ab488 100644
--- a/apio/resources/packages.json
+++ b/apio/resources/packages.json
@@ -12,7 +12,7 @@
       "extension": "zip",
       "url_version": "https://github.com/FPGAwars/apio-examples/raw/master/VERSION"
     },
-    "description": "Verilog examples",
+    "description": "Apio's project examples",
     "env": {}
   },
   "oss-cad-suite": {
@@ -28,7 +28,7 @@
       "extension": "tar.gz",
       "url_version": "https://github.com/FPGAwars/tools-oss-cad-suite/raw/main/VERSION_DEV"
     },
-    "description": "YosysHQ/oss-cad-suite",
+    "description": "YosysHQ's oss-cad-suite",
     "env": {
       "path": [
         "%p/bin",
@@ -66,6 +66,26 @@
       ]
     }
   },
+  "verible": {
+    "repository": {
+      "name": "tools-verible",
+      "organization": "FPGAwars"
+    },
+    "release": {
+      "tag_name": "v%V",
+      "compressed_name": "tools-verible-%P-%V",
+      "uncompressed_name": "",
+      "folder_name": "tools-verible",
+      "extension": "tar.gz",
+      "url_version": "https://github.com/FPGAwars/tools-verible/raw/main/VERSION_DEV"
+    },
+    "description": "Chips Aliance's Verible toolset",
+    "env": {
+      "path": [
+        "%p/bin"
+      ]
+    }
+  },
   "drivers": {
     "repository": {
       "name": "tools-drivers",
@@ -112,4 +132,4 @@
       ]
     }
   }
-}
+}
\ No newline at end of file