From 83f2eac29691735500d4d4edfd08e449db9aa621 Mon Sep 17 00:00:00 2001 From: Zapta Date: Tue, 17 Dec 2024 21:03:30 -0800 Subject: [PATCH] Added two test-examples with system-verolog code. --- .../TB/edu-ciaa-fpga/and-gate/and_gate.pcf | 3 ++ .../TB/edu-ciaa-fpga/and-gate/and_gate.sv | 9 +++++ .../edu-ciaa-fpga/and-gate/and_gate_tb.gtkw | 24 +++++++++++ .../TB/edu-ciaa-fpga/and-gate/and_gate_tb.sv | 28 +++++++++++++ .../TB/edu-ciaa-fpga/and-gate/apio.ini | 7 ++++ test-examples/TB/edu-ciaa-fpga/fdd/apio.ini | 6 +++ test-examples/TB/edu-ciaa-fpga/fdd/ffd.pcf | 8 ++++ test-examples/TB/edu-ciaa-fpga/fdd/ffd.sv | 10 +++++ .../TB/edu-ciaa-fpga/fdd/ffd_tb.gtkw | 28 +++++++++++++ test-examples/TB/edu-ciaa-fpga/fdd/ffd_tb.sv | 40 +++++++++++++++++++ 10 files changed, 163 insertions(+) create mode 100644 test-examples/TB/edu-ciaa-fpga/and-gate/and_gate.pcf create mode 100644 test-examples/TB/edu-ciaa-fpga/and-gate/and_gate.sv create mode 100644 test-examples/TB/edu-ciaa-fpga/and-gate/and_gate_tb.gtkw create mode 100644 test-examples/TB/edu-ciaa-fpga/and-gate/and_gate_tb.sv create mode 100644 test-examples/TB/edu-ciaa-fpga/and-gate/apio.ini create mode 100644 test-examples/TB/edu-ciaa-fpga/fdd/apio.ini create mode 100644 test-examples/TB/edu-ciaa-fpga/fdd/ffd.pcf create mode 100644 test-examples/TB/edu-ciaa-fpga/fdd/ffd.sv create mode 100644 test-examples/TB/edu-ciaa-fpga/fdd/ffd_tb.gtkw create mode 100644 test-examples/TB/edu-ciaa-fpga/fdd/ffd_tb.sv diff --git a/test-examples/TB/edu-ciaa-fpga/and-gate/and_gate.pcf b/test-examples/TB/edu-ciaa-fpga/and-gate/and_gate.pcf new file mode 100644 index 00000000..e3c1886b --- /dev/null +++ b/test-examples/TB/edu-ciaa-fpga/and-gate/and_gate.pcf @@ -0,0 +1,3 @@ +set_io --warn-no-port s 1 #-- output +set_io --warn-no-port a 31 # input +set_io --warn-no-port b 32 # input \ No newline at end of file diff --git a/test-examples/TB/edu-ciaa-fpga/and-gate/and_gate.sv b/test-examples/TB/edu-ciaa-fpga/and-gate/and_gate.sv new file mode 100644 index 00000000..aeaf77b7 --- /dev/null +++ b/test-examples/TB/edu-ciaa-fpga/and-gate/and_gate.sv @@ -0,0 +1,9 @@ +module and_gate ( + input logic a, + input logic b, + output logic s +); + + assign s = a & b; + +endmodule \ No newline at end of file diff --git a/test-examples/TB/edu-ciaa-fpga/and-gate/and_gate_tb.gtkw b/test-examples/TB/edu-ciaa-fpga/and-gate/and_gate_tb.gtkw new file mode 100644 index 00000000..17ea4f31 --- /dev/null +++ b/test-examples/TB/edu-ciaa-fpga/and-gate/and_gate_tb.gtkw @@ -0,0 +1,24 @@ +[*] +[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI +[*] Wed Dec 18 04:17:41 2024 +[*] +[dumpfile] "/Volumes/projects/apio-dev/repo/test-examples/TB/edu-ciaa-fpga/and-gate/_build/and_gate_tb.vcd" +[dumpfile_mtime] "Wed Dec 18 04:17:00 2024" +[dumpfile_size] 38921 +[savefile] "/Volumes/projects/apio-dev/repo/test-examples/TB/edu-ciaa-fpga/and-gate/and_gate_tb.gtkw" +[timestart] 0 +[size] 1000 600 +[pos] -1 -1 +*-20.251245 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] and_gate_testbench. +[sst_width] 253 +[signals_width] 78 +[sst_expanded] 1 +[sst_vpaned_height] 334 +@28 +and_gate_testbench.a +and_gate_testbench.b +@29 +and_gate_testbench.s +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/test-examples/TB/edu-ciaa-fpga/and-gate/and_gate_tb.sv b/test-examples/TB/edu-ciaa-fpga/and-gate/and_gate_tb.sv new file mode 100644 index 00000000..f99ceb58 --- /dev/null +++ b/test-examples/TB/edu-ciaa-fpga/and-gate/and_gate_tb.sv @@ -0,0 +1,28 @@ +`default_nettype none +`timescale 100 ns / 10 ns + +module and_gate_testbench(); + + logic a, b, s; + + // Instantiate device under test + and_gate dut(a, b, s); + + // Apply inputs one at a time + initial begin + $dumpvars(0, and_gate_testbench); + + a = 0; b = 0; + #10; + a = 0; b = 1; + #10; + a = 1; b = 0; + #10; + a = 1; b = 1; + #10; + + $display("End of simulation"); + $finish; + + end +endmodule \ No newline at end of file diff --git a/test-examples/TB/edu-ciaa-fpga/and-gate/apio.ini b/test-examples/TB/edu-ciaa-fpga/and-gate/apio.ini new file mode 100644 index 00000000..f78787a7 --- /dev/null +++ b/test-examples/TB/edu-ciaa-fpga/and-gate/apio.ini @@ -0,0 +1,7 @@ +# APIO project configuration file. For details see +# https://github.com/FPGAwars/apio/wiki/Project-configuration-file + +[env] +board = edu-ciaa-fpga +top-module = and_gate + diff --git a/test-examples/TB/edu-ciaa-fpga/fdd/apio.ini b/test-examples/TB/edu-ciaa-fpga/fdd/apio.ini new file mode 100644 index 00000000..2487063c --- /dev/null +++ b/test-examples/TB/edu-ciaa-fpga/fdd/apio.ini @@ -0,0 +1,6 @@ +# APIO project configuration file. For details see +# https://github.com/FPGAwars/apio/wiki/Project-configuration-file + +[env] +board = edu-ciaa-fpga +top-module = ffd diff --git a/test-examples/TB/edu-ciaa-fpga/fdd/ffd.pcf b/test-examples/TB/edu-ciaa-fpga/fdd/ffd.pcf new file mode 100644 index 00000000..ffd03300 --- /dev/null +++ b/test-examples/TB/edu-ciaa-fpga/fdd/ffd.pcf @@ -0,0 +1,8 @@ +#------ User LEDs ------------------------------------------------------------- +set_io --warn-no-port q 1 # output + +# ------------ User push buttons ---------------------------------------------- +set_io --warn-no-port d 31 # input + +# -------------------------- SYSTEM CLOCK ------------------------------------- +set_io --warn-no-port clk 94 # input \ No newline at end of file diff --git a/test-examples/TB/edu-ciaa-fpga/fdd/ffd.sv b/test-examples/TB/edu-ciaa-fpga/fdd/ffd.sv new file mode 100644 index 00000000..fa657dba --- /dev/null +++ b/test-examples/TB/edu-ciaa-fpga/fdd/ffd.sv @@ -0,0 +1,10 @@ +module ffd( + input logic clk, + input logic d, + output logic q +); + + always_ff @(posedge clk) + q <= d; + +endmodule \ No newline at end of file diff --git a/test-examples/TB/edu-ciaa-fpga/fdd/ffd_tb.gtkw b/test-examples/TB/edu-ciaa-fpga/fdd/ffd_tb.gtkw new file mode 100644 index 00000000..1c0efdb2 --- /dev/null +++ b/test-examples/TB/edu-ciaa-fpga/fdd/ffd_tb.gtkw @@ -0,0 +1,28 @@ +[*] +[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI +[*] Wed Dec 18 05:03:12 2024 +[*] +[dumpfile] "/Volumes/projects/apio-dev/repo/test-examples/TB/edu-ciaa-fpga/fdd/_build/ffd_tb.vcd" +[dumpfile_mtime] "Wed Dec 18 05:02:49 2024" +[dumpfile_size] 5281 +[savefile] "/Volumes/projects/apio-dev/repo/test-examples/TB/edu-ciaa-fpga/fdd/ffd_tb.gtkw" +[timestart] 0 +[size] 1000 600 +[pos] -1 -1 +*-21.710676 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] testbench. +[sst_width] 253 +[signals_width] 95 +[sst_expanded] 1 +[sst_vpaned_height] 158 +@28 +testbench.clk +testbench.d +@420 +testbench.i +@28 +testbench.i_b[1:0] +@29 +testbench.q +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/test-examples/TB/edu-ciaa-fpga/fdd/ffd_tb.sv b/test-examples/TB/edu-ciaa-fpga/fdd/ffd_tb.sv new file mode 100644 index 00000000..fcc2e4ce --- /dev/null +++ b/test-examples/TB/edu-ciaa-fpga/fdd/ffd_tb.sv @@ -0,0 +1,40 @@ +`default_nettype none +`timescale 100 ns / 10 ns + +module testbench(); + +parameter DURATION = 10; + +logic clk = 0; +always #0.5 clk = ~clk; + +logic d, q; + +ffd UUT ( + .clk(clk), + .d(d), + .q(q) +); + +integer i; +reg [1:0] i_b; + +initial begin + + $dumpvars(0, testbench); + + for (i=0; i<100; i=i+1) + begin + $display ("Current loop # %0d", i); + $display ("Current loop # %0b", i); + + #1 + i_b = i; + d = i_b[0]; + end + + #(DURATION) $display("End of simulation"); + $finish; +end + +endmodule \ No newline at end of file