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I am not 100% sure if I am right here, so apologies if I am not.
I was looking at test OpSize/66_D6.asm which has the instruction: movq xmm0, xmm2
This on NASM generates the (probably unintended) form: movq xmm0, xmm2 ; +0 = f3 0f 7e c2 (https://godbolt.org/z/ebWchEcbb)
While I assume the one that the test focuses on testing is the form: movq xmm0, xmm2 ; +0 = 66 0f d6 d0
I assume this doesn't cause any real problems, but I thought you might want to know that the test doesn't test the reg/reg form of the D6 opcode (if I am right).
This may or may not also happen on other tests that have both a xmm/xmm128 and a xmm128/xmm form where NASM compiles them to the unintended form.
The text was updated successfully, but these errors were encountered:
You're right, when I was writing the tests I probably assumed in some cases that nasm was generating the correct opcodes. I'll need to go to that test and resolve it. There's likely to be more that this happens with.
I am not 100% sure if I am right here, so apologies if I am not.
I was looking at test
OpSize/66_D6.asm
which has the instruction:movq xmm0, xmm2
This on NASM generates the (probably unintended) form:
movq xmm0, xmm2 ; +0 = f3 0f 7e c2
(https://godbolt.org/z/ebWchEcbb)While I assume the one that the test focuses on testing is the form:
movq xmm0, xmm2 ; +0 = 66 0f d6 d0
I assume this doesn't cause any real problems, but I thought you might want to know that the test doesn't test the reg/reg form of the D6 opcode (if I am right).
This may or may not also happen on other tests that have both a xmm/xmm128 and a xmm128/xmm form where NASM compiles them to the unintended form.
The text was updated successfully, but these errors were encountered: