instcountci: Generate SVE for 80bit load/stores when possible

FEX-Emu · Dec 1, 2024 · e01a568 · e01a568
1 parent dc10e49
commit e01a568
Showing 1 changed file with 25 additions and 47 deletions.
diff --git a/unittests/InstructionCountCI/X87store-SVE.json b/unittests/InstructionCountCI/X87store-SVE.json
@@ -14,16 +14,14 @@
   },
   "Instructions": {
     "fstp tword [rax]": {
-      "ExpectedInstructionCount": 15,
+      "ExpectedInstructionCount": 13,
       "Comment": "Single 80-bit store.",
       "ExpectedArm64ASM": [
         "ldrb w20, [x28, #1019]",
         "add x0, x28, x20, lsl #4",
         "ldr q2, [x0, #1040]",
-        "str d2, [x4]",
-        "mov x21, v2.d[1]",
-        "add x22, x4, #0x8 (8)",
-        "strh w21, [x22]",
+        "ptrue p0.h, vl5",
+        "st1h {z2.h}, p0, [x4]",
         "ldrb w21, [x28, #1298]",
         "mov w22, #0x1",
         "lsl w22, w22, w20",
@@ -36,7 +34,7 @@
     },
     "2-store 80bit": {
       "x86InstructionCount": 2,
-      "ExpectedInstructionCount": 29,
+      "ExpectedInstructionCount": 25,
       "x86Insts": [
         "fstp tword [rax]",
         "fstp tword [rax+10]"
@@ -45,10 +43,8 @@
         "ldrb w20, [x28, #1019]",
         "add x0, x28, x20, lsl #4",
         "ldr q2, [x0, #1040]",
-        "str d2, [x4]",
-        "mov x21, v2.d[1]",
-        "add x22, x4, #0x8 (8)",
-        "strh w21, [x22]",
+        "ptrue p0.h, vl5",
+        "st1h {z2.h}, p0, [x4]",
         "ldrb w21, [x28, #1298]",
         "mov w22, #0x1",
         "lsl w23, w22, w20",
@@ -60,10 +56,8 @@
         "add x21, x4, #0xa (10)",
         "add x0, x28, x20, lsl #4",
         "ldr q2, [x0, #1040]",
-        "str d2, [x21]",
-        "mov x23, v2.d[1]",
-        "add x21, x21, #0x8 (8)",
-        "strh w23, [x21]",
+        "ptrue p0.h, vl5",
+        "st1h {z2.h}, p0, [x21]",
         "ldrb w21, [x28, #1298]",
         "lsl w22, w22, w20",
         "bic w21, w21, w22",
@@ -75,7 +69,7 @@
     },
     "8-store 80bit": {
       "x86InstructionCount": 8,
-      "ExpectedInstructionCount": 113,
+      "ExpectedInstructionCount": 97,
       "x86Insts": [
         "fstp tword [rax]",
         "fstp tword [rax+10]",
@@ -90,10 +84,8 @@
         "ldrb w20, [x28, #1019]",
         "add x0, x28, x20, lsl #4",
         "ldr q2, [x0, #1040]",
-        "str d2, [x4]",
-        "mov x21, v2.d[1]",
-        "add x22, x4, #0x8 (8)",
-        "strh w21, [x22]",
+        "ptrue p0.h, vl5",
+        "st1h {z2.h}, p0, [x4]",
         "ldrb w21, [x28, #1298]",
         "mov w22, #0x1",
         "lsl w23, w22, w20",
@@ -105,10 +97,8 @@
         "add x21, x4, #0xa (10)",
         "add x0, x28, x20, lsl #4",
         "ldr q2, [x0, #1040]",
-        "str d2, [x21]",
-        "mov x23, v2.d[1]",
-        "add x21, x21, #0x8 (8)",
-        "strh w23, [x21]",
+        "ptrue p0.h, vl5",
+        "st1h {z2.h}, p0, [x21]",
         "ldrb w21, [x28, #1298]",
         "lsl w23, w22, w20",
         "bic w21, w21, w23",
@@ -119,10 +109,8 @@
         "add x21, x4, #0x14 (20)",
         "add x0, x28, x20, lsl #4",
         "ldr q2, [x0, #1040]",
-        "str d2, [x21]",
-        "mov x23, v2.d[1]",
-        "add x21, x21, #0x8 (8)",
-        "strh w23, [x21]",
+        "ptrue p0.h, vl5",
+        "st1h {z2.h}, p0, [x21]",
         "ldrb w21, [x28, #1298]",
         "lsl w23, w22, w20",
         "bic w21, w21, w23",
@@ -133,10 +121,8 @@
         "add x21, x4, #0x1e (30)",
         "add x0, x28, x20, lsl #4",
         "ldr q2, [x0, #1040]",
-        "str d2, [x21]",
-        "mov x23, v2.d[1]",
-        "add x21, x21, #0x8 (8)",
-        "strh w23, [x21]",
+        "ptrue p0.h, vl5",
+        "st1h {z2.h}, p0, [x21]",
         "ldrb w21, [x28, #1298]",
         "lsl w23, w22, w20",
         "bic w21, w21, w23",
@@ -147,10 +133,8 @@
         "add x21, x4, #0x28 (40)",
         "add x0, x28, x20, lsl #4",
         "ldr q2, [x0, #1040]",
-        "str d2, [x21]",
-        "mov x23, v2.d[1]",
-        "add x21, x21, #0x8 (8)",
-        "strh w23, [x21]",
+        "ptrue p0.h, vl5",
+        "st1h {z2.h}, p0, [x21]",
         "ldrb w21, [x28, #1298]",
         "lsl w23, w22, w20",
         "bic w21, w21, w23",
@@ -161,10 +145,8 @@
         "add x21, x4, #0x32 (50)",
         "add x0, x28, x20, lsl #4",
         "ldr q2, [x0, #1040]",
-        "str d2, [x21]",
-        "mov x23, v2.d[1]",
-        "add x21, x21, #0x8 (8)",
-        "strh w23, [x21]",
+        "ptrue p0.h, vl5",
+        "st1h {z2.h}, p0, [x21]",
         "ldrb w21, [x28, #1298]",
         "lsl w23, w22, w20",
         "bic w21, w21, w23",
@@ -175,10 +157,8 @@
         "add x21, x4, #0x3c (60)",
         "add x0, x28, x20, lsl #4",
         "ldr q2, [x0, #1040]",
-        "str d2, [x21]",
-        "mov x23, v2.d[1]",
-        "add x21, x21, #0x8 (8)",
-        "strh w23, [x21]",
+        "ptrue p0.h, vl5",
+        "st1h {z2.h}, p0, [x21]",
         "ldrb w21, [x28, #1298]",
         "lsl w23, w22, w20",
         "bic w21, w21, w23",
@@ -189,10 +169,8 @@
         "add x21, x4, #0x46 (70)",
         "add x0, x28, x20, lsl #4",
         "ldr q2, [x0, #1040]",
-        "str d2, [x21]",
-        "mov x23, v2.d[1]",
-        "add x21, x21, #0x8 (8)",
-        "strh w23, [x21]",
+        "ptrue p0.h, vl5",
+        "st1h {z2.h}, p0, [x21]",
         "ldrb w21, [x28, #1298]",
         "lsl w22, w22, w20",
         "bic w21, w21, w22",