diff --git a/FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.cpp b/FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.cpp
index 9c625f70a8..a59467eb5b 100644
--- a/FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.cpp
+++ b/FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.cpp
@@ -700,8 +700,10 @@ namespace {
                 // Marking here as written is overly agressive, but
                 // there might be write(s) later on the instruction stream
                 if ((*StaticMap)) {
-                  SRA_DEBUG("Markng ssa{} as written because ssa{} re-loads sra{}, and we can't track possible future writes\n",
-                            (*StaticMap) - &LiveRanges[0], Node, -1 /*vreg*/);
+                  SRA_DEBUG(
+                      "Marking ssa{} as written because ssa{} re-loads sra{}, "
+                      "and we can't track possible future writes\n",
+                      (*StaticMap) - &LiveRanges[0], Node, -1 /*vreg*/);
                   (*StaticMap)->Written = true;
                 }
 
diff --git a/FEXCore/docs/Frontend.md b/FEXCore/docs/Frontend.md
index a0733acd8b..bba484897f 100644
--- a/FEXCore/docs/Frontend.md
+++ b/FEXCore/docs/Frontend.md
@@ -2,7 +2,7 @@
 ---
 The FEXCore frontend's job is to translate an incoming x86-64 instruction stream in to a more easily digested version of x86.
 This effectively expands x86-64 instruction encodings to be more easily ingested later on in the process.
-This ends up being essential to allowing our IR translation step to be less strenious. It can decode a "common" expanded instruction format rather than various things that x86-supports.
+This ends up being essential to allowing our IR translation step to be less strenuous. It can decode a "common" expanded instruction format rather than various things that x86-supports.
 For a simple example, x86-64's primary op table has ALU ops that duplicate themselves at least six times with minor differences between each. The frontend is able to decode a large amount of these ops to the "same" op that the IR translation understands more readily.
 This works for most instructions that follow a common decoding scheme, although there are instructions that don't follow the rules and must be handled explicitly elsewhere.
 
diff --git a/FEXCore/docs/OpDispatcher.md b/FEXCore/docs/OpDispatcher.md
index 8fc4f0441e..a1a82ab115 100644
--- a/FEXCore/docs/OpDispatcher.md
+++ b/FEXCore/docs/OpDispatcher.md
@@ -32,7 +32,7 @@ BeginBlock
         %360 i64 = LoadContext 0x8, 0x58
         %392 i64 = LoadContext 0x8, 0x48
         %424 i64 = LoadContext 0x8, 0x50
-        %456 i64 = Syscall%232, %264, %296, %328, %360, %392, %424
+        %456 i64 = Syscall %232, %264, %296, %328, %360, %392, %424
         StoreContext 0x8, 0x8, %456
         BeginBlock
         EndBlock 0x1e
diff --git a/unittests/InstructionCountCI/Primary.json b/unittests/InstructionCountCI/Primary.json
index e6af1e1949..d4d8a34cc8 100644
--- a/unittests/InstructionCountCI/Primary.json
+++ b/unittests/InstructionCountCI/Primary.json
@@ -2818,7 +2818,7 @@
     },
     "cdq": {
       "ExpectedInstructionCount": 3,
-      "Comment": "0x98",
+      "Comment": "0x99",
       "ExpectedArm64ASM": [
         "mov w20, w4",
         "sbfx x20, x20, #31, #1",
@@ -2827,7 +2827,7 @@
     },
     "cqo": {
       "ExpectedInstructionCount": 1,
-      "Comment": "0x98",
+      "Comment": "0x99",
       "ExpectedArm64ASM": [
         "asr x6, x4, #63"
       ]