Merge pull request #3541 from alyssarosenzweig/opt/clc

optimize clc
FEX-Emu · Apr 1, 2024 · b1ddd8c · b1ddd8c
2 parents f2d001e + b64a594
commit b1ddd8c
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Showing 3 changed files with 18 additions and 4 deletions.
diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp b/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp
@@ -334,7 +334,7 @@ DEF_OP(RmifNZCV) {
   auto Op = IROp->C<IR::IROp_RmifNZCV>();
   LOGMAN_THROW_A_FMT(CTX->HostFeatures.SupportsFlagM, "Unsupported flagm op");
 
-  rmif(GetReg(Op->Src.ID()).X(), Op->Rotate, Op->Mask);
+  rmif(GetZeroableReg(Op->Src).X(), Op->Rotate, Op->Mask);
 }
 
 DEF_OP(SetSmallNZV) {

diff --git a/FEXCore/Source/Interface/IR/Passes/ConstProp.cpp b/FEXCore/Source/Interface/IR/Passes/ConstProp.cpp
@@ -1137,6 +1137,21 @@ bool ConstProp::ConstantInlining(IREmitter *IREmit, const IRListView& CurrentIR)
 
         break;
       }
+      case OP_RMIFNZCV:
+      {
+        auto Op = IROp->C<IR::IROp_RmifNZCV>();
+
+        uint64_t Constant1{};
+        if (IREmit->IsValueConstant(Op->Header.Args[0], &Constant1)) {
+          if (Constant1 == 0) {
+            IREmit->SetWriteCursor(CurrentIR.GetNode(Op->Header.Args[0]));
+            IREmit->ReplaceNodeArgument(CodeNode, 0, CreateInlineConstant(IREmit, 0));
+            Changed = true;
+          }
+        }
+
+        break;
+      }
       case OP_CONDADDNZCV:
       {
         auto Op = IROp->C<IR::IROp_CondAddNZCV>();

diff --git a/unittests/InstructionCountCI/FlagM/Primary.json b/unittests/InstructionCountCI/FlagM/Primary.json
@@ -2353,11 +2353,10 @@
       ]
     },
     "clc": {
-      "ExpectedInstructionCount": 2,
+      "ExpectedInstructionCount": 1,
       "Comment": "0xf8",
       "ExpectedArm64ASM": [
-        "mov w20, #0x0",
-        "rmif x20, #63, #nzCv"
+        "rmif xzr, #63, #nzCv"
       ]
     },
     "stc": {