diff --git a/core/ir/x86/decode_table.c b/core/ir/x86/decode_table.c
index bf6e4014a6d..d659e211270 100644
--- a/core/ir/x86/decode_table.c
+++ b/core/ir/x86/decode_table.c
@@ -3899,7 +3899,7 @@ const instr_info_t prefix_extensions[][12] = {
     {VEX_W_EXT, 0x660f7e10, "(vex_W ext 109)", xx, xx, xx, xx, xx, mrm|vex, x, 109},
     {INVALID, 0xf20f7e10, "(bad)", xx, xx, xx, xx, xx, no, x, NA},
     {INVALID,   0x0f7e10, "(bad)", xx, xx, xx, xx, xx, no, x, NA},
-    {OP_vmovq, 0xf30f7e10, "vmovq", Vdq, xx, Wq_dq, xx, xx, mrm|evex, x, tpe[61][6]},
+    {OP_vmovq, 0xf30f7e40, "vmovq", Vdq, xx, Wq_dq, xx, xx, mrm|evex, x, tpe[61][6]},
     {EVEX_Wb_EXT, 0x660f7e10, "(evex_Wb ext 137)", xx, xx, xx, xx, xx, mrm|evex, x, 137},
     {INVALID, 0xf20f7e10, "(bad)", xx, xx, xx, xx, xx, no, x, NA},
   }, /* prefix extension 52: all assumed to have Ib */
@@ -4041,7 +4041,7 @@ const instr_info_t prefix_extensions[][12] = {
     {INVALID, 0xf20fd610, "(bad)", xx, xx, xx, xx, xx, no, x, NA},
     {INVALID,   0x0fd610, "(bad)", xx, xx, xx, xx, xx, no, x, NA},
     {INVALID, 0xf30fd610, "(bad)", xx, xx, xx, xx, xx, no, x, NA},
-    {OP_vmovq, 0x660fd610, "vmovq", Wq_dq, xx, Vq_dq, xx, xx, mrm|evex, x, tvexw[108][1]},
+    {OP_vmovq, 0x660fd640, "vmovq", Wq_dq, xx, Vq_dq, xx, xx, mrm|evex, x, tvexw[108][1]},
     {INVALID, 0xf20fd610, "(bad)", xx, xx, xx, xx, xx, no, x, NA},
   }, /* prefix extension 62 */
   {
diff --git a/suite/tests/api/ir_x86.c b/suite/tests/api/ir_x86.c
index 641426c8fac..ba40a3f9bd6 100644
--- a/suite/tests/api/ir_x86.c
+++ b/suite/tests/api/ir_x86.c
@@ -1544,6 +1544,23 @@ test_x64_vmovq(void *dc)
                               false /*no bytes*/, dbuf, BUFFER_SIZE_ELEMENTS(dbuf), &len);
     ASSERT(pc == &b2[7]);
     ASSERT(strcmp(dbuf, "vmovq  (%rdx,%rcx)[8byte] -> %xmm25\n") == 0);
+
+    const byte expected1[] = { 0x62, 0xc1, 0xfe, 0x08, 0x7e, 0x45, 0x00 };
+    const byte expected2[] = { 0x62, 0xc1, 0xfd, 0x08, 0xd6, 0x45, 0x00 };
+
+    instr_t *instr =
+        INSTR_CREATE_vmovq(dc, opnd_create_reg(DR_REG_XMM16),
+                           opnd_create_base_disp_ex(DR_REG_R13, DR_REG_NULL, 0, 0, OPSZ_8,
+                                                    true, false, false));
+    test_instr_encode(dc, instr, 7);
+    ASSERT(!memcmp(expected1, buf, 7));
+
+    instr = INSTR_CREATE_vmovq(dc,
+                               opnd_create_base_disp_ex(DR_REG_R13, DR_REG_NULL, 0, 0,
+                                                        OPSZ_8, true, false, false),
+                               opnd_create_reg_partial(DR_REG_XMM16, OPSZ_8));
+    test_instr_encode(dc, instr, 7);
+    ASSERT(!memcmp(expected2, buf, 7));
 }
 #endif