diff --git a/clients/drcachesim/reader/reader.cpp b/clients/drcachesim/reader/reader.cpp
index 616192ce16e..06d73fe8ac9 100644
--- a/clients/drcachesim/reader/reader.cpp
+++ b/clients/drcachesim/reader/reader.cpp
@@ -138,6 +138,8 @@ reader_t::operator++()
                 cur_ref_.instr.addr = cur_pc_;
                 next_pc_ = cur_pc_ + cur_ref_.instr.size;
                 prev_instr_addr_ = input_entry_->addr;
+                if (cur_ref_.instr.type != TRACE_TYPE_INSTR_NO_FETCH)
+                    ++cur_instr_count_;
             }
             break;
         case TRACE_TYPE_INSTR_BUNDLE:
@@ -225,17 +227,21 @@ reader_t::operator++()
             // cached timestamp and cpu as do linear portion of seek, and then emit
             // cached top-level headers plus the last timestamp+cpu at the target
             // point.
-            if (cur_ref_.marker.marker_type == TRACE_MARKER_TYPE_TIMESTAMP &&
-                cur_ref_.marker.marker_value == last_timestamp_) {
+            if (chunk_instr_count_ > 0 &&
+                cur_ref_.marker.marker_type == TRACE_MARKER_TYPE_TIMESTAMP &&
+                cur_instr_count_ / chunk_instr_count_ !=
+                    last_timestamp_instr_count_ / chunk_instr_count_) {
                 skip_next_cpu_ = true;
             } else if (cur_ref_.marker.marker_type == TRACE_MARKER_TYPE_CPU_ID &&
                        skip_next_cpu_) {
                 skip_next_cpu_ = false;
             } else {
-                if (cur_ref_.marker.marker_type == TRACE_MARKER_TYPE_TIMESTAMP)
-                    last_timestamp_ = cur_ref_.marker.marker_value;
                 have_memref = true;
             }
+            if (cur_ref_.marker.marker_type == TRACE_MARKER_TYPE_TIMESTAMP)
+                last_timestamp_instr_count_ = cur_instr_count_;
+            else if (cur_ref_.marker.marker_type == TRACE_MARKER_TYPE_CHUNK_INSTR_COUNT)
+                chunk_instr_count_ = cur_ref_.marker.marker_value;
             break;
         default:
             ERRMSG("Unknown trace entry type %d\n", input_entry_->type);
diff --git a/clients/drcachesim/reader/reader.h b/clients/drcachesim/reader/reader.h
index b8e5aa5ce62..d7ec06715ba 100644
--- a/clients/drcachesim/reader/reader.h
+++ b/clients/drcachesim/reader/reader.h
@@ -143,7 +143,9 @@ class reader_t : public std::iterator<std::input_iterator_tag, memref_t> {
     addr_t prev_instr_addr_ = 0;
     int bundle_idx_ = 0;
     std::unordered_map<memref_tid_t, memref_pid_t> tid2pid_;
-    uint64_t last_timestamp_ = 0;
+    uint64_t cur_instr_count_ = 0;
+    uint64_t chunk_instr_count_ = 0; // Unchanging once set to non-zero.
+    uint64_t last_timestamp_instr_count_ = 0;
     bool skip_next_cpu_ = false;
 };