diff --git a/core/ir/aarch64/codec.txt b/core/ir/aarch64/codec.txt index ff08083d8a8..f8ed1c5aa1b 100644 --- a/core/ir/aarch64/codec.txt +++ b/core/ir/aarch64/codec.txt @@ -1162,20 +1162,30 @@ x101101011000000000101xxxxxxxxxx cls wx0 : wx5 1001111001111000000000xxxxxxxxxx fcvtzs x0 : d5 x001111000111001000000xxxxxxxxxx fcvtzu wx0 : s5 x001111001111001000000xxxxxxxxxx fcvtzu wx0 : d5 -x001111000011001xxxxxxxxxxxxxxxx fcvtzu wx0 : s5 scale -x001111001011001xxxxxxxxxxxxxxxx fcvtzu wx0 : d5 scale # Floating-point convert (vector, integer) (vector single-precision and double-precision) 0101111010100001101110xxxxxxxxxx fcvtzs s0 : s5 0101111011100001101110xxxxxxxxxx fcvtzs d0 : d5 0111111010100001101110xxxxxxxxxx fcvtzu s0 : s5 0111111011100001101110xxxxxxxxxx fcvtzu d0 : d5 -0111111100xxxxxx111111xxxxxxxxxx fcvtzu s0 : s5 immhb -0111111101xxxxxx111111xxxxxxxxxx fcvtzu d0 : d5 immhb # Floating-point convert (vector, integer) (scalar single-precision and double-precision) 0x0011101x100001101110xxxxxxxxxx fcvtzs dq0 : dq5 sd_sz 0x1011101x100001101110xxxxxxxxxx fcvtzu dq0 : dq5 sd_sz + +# Floating-point convert (scalar, fixed-point) +x001111000011000xxxxxxxxxxxxxxxx fcvtzs wx0 : s5 scale +x001111001011000xxxxxxxxxxxxxxxx fcvtzs wx0 : d5 scale +x001111000011001xxxxxxxxxxxxxxxx fcvtzu wx0 : s5 scale +x001111001011001xxxxxxxxxxxxxxxx fcvtzu wx0 : d5 scale + +# Floating-point convert (vector, fixed-point) (scalar) +0101111100xxxxxx111111xxxxxxxxxx fcvtzs s0 : s5 immhb +0101111101xxxxxx111111xxxxxxxxxx fcvtzs d0 : d5 immhb +0111111100xxxxxx111111xxxxxxxxxx fcvtzu s0 : s5 immhb +0111111101xxxxxx111111xxxxxxxxxx fcvtzu d0 : d5 immhb + +# Float-point convert (vector, fixed-point) (vector) 0x1011110xxxxxxx111111xxxxxxxxxx fcvtzu dq0 : dq5 sd_sz immhb # Floating-point data-processing (2 source) diff --git a/core/ir/aarch64/instr_create_api.h b/core/ir/aarch64/instr_create_api.h index df98542e66c..b985ef4a7c0 100644 --- a/core/ir/aarch64/instr_create_api.h +++ b/core/ir/aarch64/instr_create_api.h @@ -1859,6 +1859,18 @@ enum { #define INSTR_CREATE_fcvtzs_scalar(dc, Rd, Rm) \ instr_create_1dst_1src(dc, OP_fcvtzs, Rd, Rm) +/** + * Creates an FCVTZS scalar floating-point to fixed-point convert instruction. + * \param dc The void * dcontext used to allocate memory for the #instr_t. + * \param Rd Floating-point or integer output register. + * \param Rm Floating-point input register. + * \param fbits The number of bits after the binary point in the fixed-point + * destination. + */ + +#define INSTR_CREATE_fcvtzs_scalar_fixed(dc, Rd, Rm, fbits) \ + instr_create_1dst_2src(dc, OP_fcvtzs, Rd, Rm, fbits) + /** * Creates an FCVTZU floating point instruction. * \param dc The void * dcontext used to allocate memory for the #instr_t. diff --git a/suite/tests/api/dis-a64.txt b/suite/tests/api/dis-a64.txt index 6f46f46368a..7df4cf03bee 100644 --- a/suite/tests/api/dis-a64.txt +++ b/suite/tests/api/dis-a64.txt @@ -2200,6 +2200,27 @@ fd7fffff : ldr d31, [sp,#32760] : ldr +0x7ff8(%sp)[8byte] -> %d31 7ee1b841 : fcvtzu d1, d2 : fcvtzu %d2 -> %d1 # Floating-point/fixed-point conversion +1e18f107 : fcvtzs w7, s8, #4 : fcvtzs %s8 $0x04 -> %w7 +9e18c2ad : fcvtzs x13, s21, #16 : fcvtzs %s21 $0x10 -> %x13 +1e58813e : fcvtzs w30, d9, #32 : fcvtzs %d9 $0x20 -> %w30 +9e5801ec : fcvtzs x12, d15, #64 : fcvtzs %d15 $0x40 -> %x12 +5f3ffc20 : fcvtzs s0, s1, #1 : fcvtzs %s1 $0x01 -> %s0 +5f3efc62 : fcvtzs s2, s3, #2 : fcvtzs %s3 $0x02 -> %s2 +5f3cfca4 : fcvtzs s4, s5, #4 : fcvtzs %s5 $0x04 -> %s4 +5f38fce6 : fcvtzs s6, s7, #8 : fcvtzs %s7 $0x08 -> %s6 +5f30fd28 : fcvtzs s8, s9, #16 : fcvtzs %s9 $0x10 -> %s8 +5f20fd6a : fcvtzs s10, s11, #32 : fcvtzs %s11 $0x20 -> %s10 +5f2bffbc : fcvtzs s28, s29, #21 : fcvtzs %s29 $0x15 -> %s28 +5f21fffe : fcvtzs s30, s31, #31 : fcvtzs %s31 $0x1f -> %s30 +5f7ffc20 : fcvtzs d0, d1, #1 : fcvtzs %d1 $0x01 -> %d0 +5f7cfca4 : fcvtzs d4, d5, #4 : fcvtzs %d5 $0x04 -> %d4 +5f78fce6 : fcvtzs d6, d7, #8 : fcvtzs %d7 $0x08 -> %d6 +5f70fd28 : fcvtzs d8, d9, #16 : fcvtzs %d9 $0x10 -> %d8 +5f60fd6a : fcvtzs d10, d11, #32 : fcvtzs %d11 $0x20 -> %d10 +5f40fdac : fcvtzs d12, d13, #64 : fcvtzs %d13 $0x40 -> %d12 +5f6bffbc : fcvtzs d28, d29, #21 : fcvtzs %d29 $0x15 -> %d28 +5f56fffe : fcvtzs d30, d31, #42 : fcvtzs %d31 $0x2a -> %d30 + 1e19f107 : fcvtzu w7, s8, #4 : fcvtzu %s8 $0x04 -> %w7 9e19c2ad : fcvtzu x13, s21, #16 : fcvtzu %s21 $0x10 -> %x13 1e59813e : fcvtzu w30, d9, #32 : fcvtzu %d9 $0x20 -> %w30 diff --git a/suite/tests/api/ir_aarch64.c b/suite/tests/api/ir_aarch64.c index b6a13891b8a..ed2ec8c151d 100644 --- a/suite/tests/api/ir_aarch64.c +++ b/suite/tests/api/ir_aarch64.c @@ -4908,6 +4908,128 @@ test_fcvtzs_vector(void *dc) opnd_create_reg(DR_REG_D7)); test_instr_encoding(dc, OP_fcvtzs, instr); } +static void +test_fcvtzs_scalar_fixed_gpr(void *dc) +{ + instr_t *instr; + + /* FCVTZS , , # */ + instr = INSTR_CREATE_fcvtzs_scalar_fixed(dc, opnd_create_reg(DR_REG_W7), + opnd_create_reg(DR_REG_S8), + opnd_create_immed_int(4, OPSZ_6b)); + test_instr_encoding(dc, OP_fcvtzs, instr); + + /* FCVTZS , , # */ + instr = INSTR_CREATE_fcvtzs_scalar_fixed(dc, opnd_create_reg(DR_REG_X13), + opnd_create_reg(DR_REG_S21), + opnd_create_immed_int(16, OPSZ_6b)); + test_instr_encoding(dc, OP_fcvtzs, instr); + + /* FCVTZS , , # */ + instr = INSTR_CREATE_fcvtzs_scalar_fixed(dc, opnd_create_reg(DR_REG_W30), + opnd_create_reg(DR_REG_D9), + opnd_create_immed_int(32, OPSZ_6b)); + test_instr_encoding(dc, OP_fcvtzs, instr); + + /* FCVTZS , , # */ + instr = INSTR_CREATE_fcvtzs_scalar_fixed(dc, opnd_create_reg(DR_REG_X12), + opnd_create_reg(DR_REG_D15), + opnd_create_immed_int(64, OPSZ_6b)); + test_instr_encoding(dc, OP_fcvtzs, instr); +} + +static void +test_fcvtzs_scalar_fixed(void *dc) +{ + instr_t *instr; + + /* FCVTZS , , # */ + instr = INSTR_CREATE_fcvtzs_scalar_fixed(dc, opnd_create_reg(DR_REG_S0), + opnd_create_reg(DR_REG_S1), + opnd_create_immed_int(1, OPSZ_6b)); + test_instr_encoding(dc, OP_fcvtzs, instr); + + instr = INSTR_CREATE_fcvtzs_scalar_fixed(dc, opnd_create_reg(DR_REG_S2), + opnd_create_reg(DR_REG_S3), + opnd_create_immed_int(2, OPSZ_6b)); + test_instr_encoding(dc, OP_fcvtzs, instr); + + instr = INSTR_CREATE_fcvtzs_scalar_fixed(dc, opnd_create_reg(DR_REG_S4), + opnd_create_reg(DR_REG_S5), + opnd_create_immed_int(4, OPSZ_6b)); + test_instr_encoding(dc, OP_fcvtzs, instr); + + instr = INSTR_CREATE_fcvtzs_scalar_fixed(dc, opnd_create_reg(DR_REG_S6), + opnd_create_reg(DR_REG_S7), + opnd_create_immed_int(8, OPSZ_6b)); + test_instr_encoding(dc, OP_fcvtzs, instr); + + instr = INSTR_CREATE_fcvtzs_scalar_fixed(dc, opnd_create_reg(DR_REG_S8), + opnd_create_reg(DR_REG_S9), + opnd_create_immed_int(16, OPSZ_6b)); + test_instr_encoding(dc, OP_fcvtzs, instr); + + instr = INSTR_CREATE_fcvtzs_scalar_fixed(dc, opnd_create_reg(DR_REG_S10), + opnd_create_reg(DR_REG_S11), + opnd_create_immed_int(32, OPSZ_6b)); + test_instr_encoding(dc, OP_fcvtzs, instr); + + instr = INSTR_CREATE_fcvtzs_scalar_fixed(dc, opnd_create_reg(DR_REG_S28), + opnd_create_reg(DR_REG_S29), + opnd_create_immed_int(21, OPSZ_6b)); + test_instr_encoding(dc, OP_fcvtzs, instr); + + instr = INSTR_CREATE_fcvtzs_scalar_fixed(dc, opnd_create_reg(DR_REG_S30), + opnd_create_reg(DR_REG_S31), + opnd_create_immed_int(31, OPSZ_6b)); + test_instr_encoding(dc, OP_fcvtzs, instr); + + /* FCVTZS
, , # */ + instr = INSTR_CREATE_fcvtzs_scalar_fixed(dc, opnd_create_reg(DR_REG_D0), + opnd_create_reg(DR_REG_D1), + opnd_create_immed_int(1, OPSZ_6b)); + test_instr_encoding(dc, OP_fcvtzs, instr); + + instr = INSTR_CREATE_fcvtzs_scalar_fixed(dc, opnd_create_reg(DR_REG_D2), + opnd_create_reg(DR_REG_D3), + opnd_create_immed_int(2, OPSZ_6b)); + test_instr_encoding(dc, OP_fcvtzs, instr); + + instr = INSTR_CREATE_fcvtzs_scalar_fixed(dc, opnd_create_reg(DR_REG_D4), + opnd_create_reg(DR_REG_D5), + opnd_create_immed_int(4, OPSZ_6b)); + test_instr_encoding(dc, OP_fcvtzs, instr); + + instr = INSTR_CREATE_fcvtzs_scalar_fixed(dc, opnd_create_reg(DR_REG_D6), + opnd_create_reg(DR_REG_D7), + opnd_create_immed_int(8, OPSZ_6b)); + test_instr_encoding(dc, OP_fcvtzs, instr); + + instr = INSTR_CREATE_fcvtzs_scalar_fixed(dc, opnd_create_reg(DR_REG_D8), + opnd_create_reg(DR_REG_D9), + opnd_create_immed_int(16, OPSZ_6b)); + test_instr_encoding(dc, OP_fcvtzs, instr); + + instr = INSTR_CREATE_fcvtzs_scalar_fixed(dc, opnd_create_reg(DR_REG_D10), + opnd_create_reg(DR_REG_D11), + opnd_create_immed_int(32, OPSZ_6b)); + test_instr_encoding(dc, OP_fcvtzs, instr); + + instr = INSTR_CREATE_fcvtzs_scalar_fixed(dc, opnd_create_reg(DR_REG_D12), + opnd_create_reg(DR_REG_D13), + opnd_create_immed_int(64, OPSZ_6b)); + test_instr_encoding(dc, OP_fcvtzs, instr); + + instr = INSTR_CREATE_fcvtzs_scalar_fixed(dc, opnd_create_reg(DR_REG_D28), + opnd_create_reg(DR_REG_D29), + opnd_create_immed_int(21, OPSZ_6b)); + test_instr_encoding(dc, OP_fcvtzs, instr); + + instr = INSTR_CREATE_fcvtzs_scalar_fixed(dc, opnd_create_reg(DR_REG_D30), + opnd_create_reg(DR_REG_D31), + opnd_create_immed_int(42, OPSZ_6b)); + test_instr_encoding(dc, OP_fcvtzs, instr); +} static void test_fcvtzu_scalar(void *dc) @@ -5331,6 +5453,12 @@ main(int argc, char *argv[]) test_fcvtzs_vector(dcontext); print("test_fcvtzs_vector complete\n"); + test_fcvtzs_scalar_fixed_gpr(dcontext); + print("test_fcvtzs_scalar_fixed_gpr complete\n"); + + test_fcvtzs_scalar_fixed(dcontext); + print("test_fcvtzs_scalar_fixed complete\n"); + test_fcvtzu_scalar(dcontext); print("test_fcvtzu_scalar complete\n"); diff --git a/suite/tests/api/ir_aarch64.expect b/suite/tests/api/ir_aarch64.expect index 0c2fbbad7f7..91925328e56 100644 --- a/suite/tests/api/ir_aarch64.expect +++ b/suite/tests/api/ir_aarch64.expect @@ -921,6 +921,29 @@ fcvtzs %s3 -> %s3 fcvtzs %d7 -> %d17 test_fcvtzs_vector complete fcvtzu %s8 -> %w7 +fcvtzs %s8 $0x04 -> %w7 +fcvtzs %s21 $0x10 -> %x13 +fcvtzs %d9 $0x20 -> %w30 +fcvtzs %d15 $0x40 -> %x12 +test_fcvtzs_scalar_fixed_gpr complete +fcvtzs %s1 $0x01 -> %s0 +fcvtzs %s3 $0x02 -> %s2 +fcvtzs %s5 $0x04 -> %s4 +fcvtzs %s7 $0x08 -> %s6 +fcvtzs %s9 $0x10 -> %s8 +fcvtzs %s11 $0x20 -> %s10 +fcvtzs %s29 $0x15 -> %s28 +fcvtzs %s31 $0x1f -> %s30 +fcvtzs %d1 $0x01 -> %d0 +fcvtzs %d3 $0x02 -> %d2 +fcvtzs %d5 $0x04 -> %d4 +fcvtzs %d7 $0x08 -> %d6 +fcvtzs %d9 $0x10 -> %d8 +fcvtzs %d11 $0x20 -> %d10 +fcvtzs %d13 $0x40 -> %d12 +fcvtzs %d29 $0x15 -> %d28 +fcvtzs %d31 $0x2a -> %d30 +test_fcvtzs_scalar_fixed complete fcvtzu %s21 -> %x13 fcvtzu %d9 -> %w0 fcvtzu %d12 -> %x12