From 08f7e32a6ec132649aee2b586a9356a95320c5d8 Mon Sep 17 00:00:00 2001 From: Kor Nielsen Date: Wed, 26 Apr 2023 23:56:55 -0700 Subject: [PATCH] Support RISC-V unaligned-scalar-mem target feature This adds `unaligned-scalar-mem` as an allowed RISC-V target feature. Some RISC-V cores support unaligned access to memory without trapping. On such cores, the compiler could significantly improve code-size and performance when using functions like core::ptr::read_unaligned by emitting a single load or store instruction with an unaligned address, rather than a long sequence of byte load/store/bitmanip instructions. Enabling the `unaligned-scalar-mem` target feature allows LLVM to do this optimization. Fixes #110883 --- compiler/rustc_codegen_ssa/src/target_features.rs | 1 + 1 file changed, 1 insertion(+) diff --git a/compiler/rustc_codegen_ssa/src/target_features.rs b/compiler/rustc_codegen_ssa/src/target_features.rs index 611dd3d1cd18a..df3d0811879cf 100644 --- a/compiler/rustc_codegen_ssa/src/target_features.rs +++ b/compiler/rustc_codegen_ssa/src/target_features.rs @@ -252,6 +252,7 @@ const RISCV_ALLOWED_FEATURES: &[(&str, Option)] = &[ ("f", Some(sym::riscv_target_feature)), ("m", Some(sym::riscv_target_feature)), ("relax", Some(sym::riscv_target_feature)), + ("unaligned-scalar-mem", Some(sym::riscv_target_feature)), ("v", Some(sym::riscv_target_feature)), ("zba", Some(sym::riscv_target_feature)), ("zbb", Some(sym::riscv_target_feature)),