add9bits.sv.bak

module add9bits (A, B, Overflow);
	input [8:0] A, B;
	//input clk, Reset;
	//output [9:0] out;
	output Overflow;
	wire [9:0]C, S;

	//assign S[9] = C[8];
	assign Overflow = C[7] ^ C[8];

	adder a1 (A[0],B[0],0,C[0],S[0]);
	adder a2 (A[1],B[1],C[0],C[1],S[1]);
	adder a3 (A[2],B[2],C[1],C[2],S[2]);
	adder a4 (A[3],B[3],C[2],C[3],S[3]);
	adder a5 (A[4],B[4],C[3],C[4],S[4]);
	adder a6 (A[5],B[5],C[4],C[5],S[5]);
	adder a7 (A[6],B[6],C[5],C[6],S[6]);
	adder a8 (A[7],B[7],C[6],C[7],S[7]);
	adder a9 (A[8],B[8],C[7],C[8],S[8]);

endmodule

module adder (A, B, CI, CO, S);
	input A,B,CI;
	output S,CO;

	assign CO = ( A & B ) |  ( CI & ( A | B ) );
	assign S = (A^B)^CI;
endmodule