Fred.sv.bak

module Fred (HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, KEY, LEDR, SW);
   output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;
   output [9:0] LEDR;
   input [3:0] KEY;
   input [9:0] SW;
	
	always @(*)
		case (SW[2:0])
			3'b000: HEX2 = 7'b1111111; // B (0000000)
					  HEX1 = 7'b1110111; // A (0001000)
					  HEX0 = 7'b0111101; // G (1000010)
					  
			3'b001: HEX2 = 7'b0111110; // U (1000001)
					  HEX1 = 7'b1101101; // S (0010010)
					  HEX0 = 7'b1111111; // B (0000000)
					  
			3'b011: HEX3 = 7'b0111111; // D (1000000)
			        HEX2 = 7'b0000110; // I (1111001)
					  HEX1 = 7'b0111001; // C (1000110)
					  HEX0 = 7'b1111001; // E (0000110)
					  
			3'b100: HEX3 = 7'b1111111; // B (0000000)
			        HEX2 = 7'b1110111; // A (0001000)
					  HEX1 = 7'b0111000; // L (1000111)
					  HEX0 = 7'b0111000; // L (1000111)
					  
			3'b101: HEX2 = 7'b0111001; // C (1000110)
					  HEX1 = 7'b1110111; // A (0001000)
					  HEX0 = 7'b0111000; // L (1000111)
					  
			3'b110: HEX3 = 7'b1101101; // S (0010010)
			        HEX2 = 7'b0111111; // O (1000000)
					  HEX1 = 7'b0111110; // U (1000001)
					  HEX0 = 7'b1110011; // P (0001100)
			default: leds = 7'bX;
		endcase
endmodule

module Fred_testbench();
	wire [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;
	wire [9:0] LEDR;
	reg [3:0] KEY;
	reg [9:0] SW;

	Fred dut (.HEX0, .HEX1, .HEX2, .HEX3, .HEX4, .HEX5, .KEY, .LEDR,
	.SW);

// Try all combinations of inputs.
	integer i;
		initial begin
		SW[3] = 1'b0;
		SW[4] = 1'b0;
		SW[5] = 1'b0;
		SW[6] = 1'b0;
		SW[7] = 1'b0;
		SW[8] = 1'b0;
		SW[9] = 1'b0;
		for(i = 0; i <8; i++) begin
			SW[2:0] = i; #10;
		end
	end
endmodule