From d13246aae504dc1e4f42c4bc314c35bc0aaac1d6 Mon Sep 17 00:00:00 2001 From: Mads Ynddal Date: Sun, 15 Sep 2024 11:29:20 +0200 Subject: [PATCH] Fix timer for Blargg interrupt test? --- pyboy/core/timer.pxd | 2 -- pyboy/core/timer.py | 10 ++++------ 2 files changed, 4 insertions(+), 8 deletions(-) diff --git a/pyboy/core/timer.pxd b/pyboy/core/timer.pxd index f36d8e831..b444294e8 100644 --- a/pyboy/core/timer.pxd +++ b/pyboy/core/timer.pxd @@ -24,8 +24,6 @@ cdef class Timer: cdef void reset(self) noexcept nogil @cython.locals(divider=cython.int) cdef bint tick(self, uint64_t) noexcept nogil - @cython.locals(divider=cython.int, cyclesleft=cython.uint) - cdef int64_t cycles_to_interrupt(self) noexcept nogil cdef void save_state(self, IntIOInterface) noexcept cdef void load_state(self, IntIOInterface, int) noexcept diff --git a/pyboy/core/timer.py b/pyboy/core/timer.py index 03138d0aa..2234addd9 100644 --- a/pyboy/core/timer.py +++ b/pyboy/core/timer.py @@ -41,6 +41,7 @@ def tick(self, _cycles): if cycles == 0: return False self.last_cycles = _cycles + self.DIV_counter += cycles self.DIV += (self.DIV_counter >> 8) # Add overflown bits to DIV self.DIV_counter &= 0xFF # Remove the overflown bits @@ -54,21 +55,18 @@ def tick(self, _cycles): divider = self.dividers[self.TAC & 0b11] ret = False - if self.TIMA_counter >= 1 << divider: - self.TIMA_counter -= 1 << divider # Keeps possible remainder + while self.TIMA_counter >= (1 << divider): + self.TIMA_counter -= (1 << divider) # Keeps possible remainder self.TIMA += 1 if self.TIMA > 0xFF: self.TIMA = self.TMA self.TIMA &= 0xFF ret = True - # return True + # self._cycles_to_interrupt = ((0x100 - self.TIMA) * (1 << divider)) - self.TIMA_counter self._cycles_to_interrupt = ((0x100 - self.TIMA) << divider) - self.TIMA_counter return ret - def cycles_to_interrupt(self): - return self._cycles_to_interrupt - def save_state(self, f): f.write(self.DIV) f.write(self.TIMA)