diff --git a/tests/refdesigns/aws_f1/1activator_125.json b/tests/refdesigns/aws_f1/1activator_125.json new file mode 100644 index 00000000..c190e6a2 --- /dev/null +++ b/tests/refdesigns/aws_f1/1activator_125.json @@ -0,0 +1,4 @@ +{ + "FpgaImageId": "afi-09259c605b16df7fb", + "FpgaImageGlobalId": "agfi-0faf0e3531f0a6dc9" +} \ No newline at end of file diff --git a/tests/refdesigns/aws_f1/1activator_axi4_125.json b/tests/refdesigns/aws_f1/1activator_axi4_125.json deleted file mode 100644 index e1fd7036..00000000 --- a/tests/refdesigns/aws_f1/1activator_axi4_125.json +++ /dev/null @@ -1,4 +0,0 @@ -{ - "FpgaImageId": "afi-037f916cc7f477bd5", - "FpgaImageGlobalId": "agfi-0069dd4744c95ee25" -} \ No newline at end of file diff --git a/tests/refdesigns/aws_f1/bad_product_id.json b/tests/refdesigns/aws_f1/1activator_bad_product_id.json similarity index 100% rename from tests/refdesigns/aws_f1/bad_product_id.json rename to tests/refdesigns/aws_f1/1activator_bad_product_id.json diff --git a/tests/refdesigns/aws_f1/empty_product_id.json b/tests/refdesigns/aws_f1/1activator_empty_product_id.json similarity index 100% rename from tests/refdesigns/aws_f1/empty_product_id.json rename to tests/refdesigns/aws_f1/1activator_empty_product_id.json diff --git a/tests/refdesigns/aws_f1/2activator_125.json b/tests/refdesigns/aws_f1/2activator_125.json new file mode 100644 index 00000000..33138f56 --- /dev/null +++ b/tests/refdesigns/aws_f1/2activator_125.json @@ -0,0 +1,4 @@ +{ + "FpgaImageId": "afi-06fc8ba0029452b5c", + "FpgaImageGlobalId": "agfi-01df1330a9a038df5" +} \ No newline at end of file diff --git a/tests/refdesigns/aws_f1/2activator_15_125.json b/tests/refdesigns/aws_f1/2activator_15_125.json new file mode 100644 index 00000000..5f7350fb --- /dev/null +++ b/tests/refdesigns/aws_f1/2activator_15_125.json @@ -0,0 +1,4 @@ +{ + "FpgaImageId": "afi-0c52d661aacb5dd87", + "FpgaImageGlobalId": "agfi-0ebeb11121501c204" +} \ No newline at end of file diff --git a/tests/refdesigns/aws_f1/2activator_250_75_swap_activator.json b/tests/refdesigns/aws_f1/2activator_250_75_swap_activator.json new file mode 100644 index 00000000..e4d80dca --- /dev/null +++ b/tests/refdesigns/aws_f1/2activator_250_75_swap_activator.json @@ -0,0 +1,4 @@ +{ + "FpgaImageId": "afi-071708dc76f8061ac", + "FpgaImageGlobalId": "agfi-0957864a7d58e235c" +} \ No newline at end of file diff --git a/tests/refdesigns/aws_f1/2activator_axi4_125.json b/tests/refdesigns/aws_f1/2activator_axi4_125.json deleted file mode 100644 index bfade19d..00000000 --- a/tests/refdesigns/aws_f1/2activator_axi4_125.json +++ /dev/null @@ -1,4 +0,0 @@ -{ - "FpgaImageId": "afi-0b03d59ba16d226f0", - "FpgaImageGlobalId": "agfi-0bd9d6d0d7aba8dba" -} \ No newline at end of file diff --git a/tests/refdesigns/aws_f1/2activator_axi4_250_125.json b/tests/refdesigns/aws_f1/2activator_axi4_250_125.json deleted file mode 100644 index 094fe0cb..00000000 --- a/tests/refdesigns/aws_f1/2activator_axi4_250_125.json +++ /dev/null @@ -1,4 +0,0 @@ -{ - "FpgaImageId": "afi-0a35fc61e6bacddad", - "FpgaImageGlobalId": "agfi-071ecd97cf7594231" -} \ No newline at end of file diff --git a/tests/refdesigns/aws_f1/2activator_axi4_swap_activator_250_125.json b/tests/refdesigns/aws_f1/2activator_axi4_swap_activator_250_125.json deleted file mode 100644 index a6810729..00000000 --- a/tests/refdesigns/aws_f1/2activator_axi4_swap_activator_250_125.json +++ /dev/null @@ -1,4 +0,0 @@ -{ - "FpgaImageId": "afi-0c324be938acb6837", - "FpgaImageGlobalId": "agfi-0f169b707346a203d" -} \ No newline at end of file diff --git a/tests/refdesigns/aws_f1/2activator_axi4_vhdl_125.json b/tests/refdesigns/aws_f1/2activator_axi4_vhdl_125.json deleted file mode 100644 index fa4ebfd1..00000000 --- a/tests/refdesigns/aws_f1/2activator_axi4_vhdl_125.json +++ /dev/null @@ -1,4 +0,0 @@ -{ - "FpgaImageId": "afi-06f2cff83432a92a2", - "FpgaImageGlobalId": "agfi-0747b02ea88543725" -} \ No newline at end of file diff --git a/tests/refdesigns/aws_f1/2activator_2clk_missing_1activator.json b/tests/refdesigns/aws_f1/2activator_missing_1activator.json similarity index 100% rename from tests/refdesigns/aws_f1/2activator_2clk_missing_1activator.json rename to tests/refdesigns/aws_f1/2activator_missing_1activator.json diff --git a/tests/refdesigns/aws_f1/2activator_vhdl_125.json b/tests/refdesigns/aws_f1/2activator_vhdl_125.json new file mode 100644 index 00000000..7f86218f --- /dev/null +++ b/tests/refdesigns/aws_f1/2activator_vhdl_125.json @@ -0,0 +1,4 @@ +{ + "FpgaImageId": "afi-03b527fb67a79e2df", + "FpgaImageGlobalId": "agfi-0ec2ac648033a27df" +} \ No newline at end of file diff --git a/tests/refdesigns/aws_f1/2activator_vhdl_15_225.json b/tests/refdesigns/aws_f1/2activator_vhdl_15_225.json new file mode 100644 index 00000000..3de554c2 --- /dev/null +++ b/tests/refdesigns/aws_f1/2activator_vhdl_15_225.json @@ -0,0 +1,4 @@ +{ + "FpgaImageId": "afi-06b2b0fb19197b51b", + "FpgaImageGlobalId": "agfi-07691b0bba2418a3e" +} \ No newline at end of file diff --git a/tests/refdesigns/aws_f1/v7.0.0.0-fix.json b/tests/refdesigns/aws_f1/v7.0.0.0-fix.json deleted file mode 100644 index 094fe0cb..00000000 --- a/tests/refdesigns/aws_f1/v7.0.0.0-fix.json +++ /dev/null @@ -1,4 +0,0 @@ -{ - "FpgaImageId": "afi-0a35fc61e6bacddad", - "FpgaImageGlobalId": "agfi-071ecd97cf7594231" -} \ No newline at end of file diff --git a/tests/refdesigns/aws_f1/v7.0.0.0.json b/tests/refdesigns/aws_f1/v7.0.0.0.json new file mode 100644 index 00000000..5f7350fb --- /dev/null +++ b/tests/refdesigns/aws_f1/v7.0.0.0.json @@ -0,0 +1,4 @@ +{ + "FpgaImageId": "afi-0c52d661aacb5dd87", + "FpgaImageGlobalId": "agfi-0ebeb11121501c204" +} \ No newline at end of file diff --git a/tests/refdesigns/aws_xrt/v7.0.0.0-fix.awsxclbin b/tests/refdesigns/aws_xrt/v7.0.0.0-fix.awsxclbin deleted file mode 100644 index c7ad39ed..00000000 Binary files a/tests/refdesigns/aws_xrt/v7.0.0.0-fix.awsxclbin and /dev/null differ diff --git a/tests/refdesigns/aws_xrt/v7.0.0.0.awsxclbin b/tests/refdesigns/aws_xrt/v7.0.0.0.awsxclbin index 0c57d549..d145900a 100644 Binary files a/tests/refdesigns/aws_xrt/v7.0.0.0.awsxclbin and b/tests/refdesigns/aws_xrt/v7.0.0.0.awsxclbin differ diff --git a/tests/refdesigns/aws_xrt/vitis_1activator_125_som.awsxclbin b/tests/refdesigns/aws_xrt/vitis_1activator_125_som.awsxclbin deleted file mode 100644 index e669c387..00000000 Binary files a/tests/refdesigns/aws_xrt/vitis_1activator_125_som.awsxclbin and /dev/null differ diff --git a/tests/refdesigns/aws_xrt/vitis_1activator_200_125.awsxclbin b/tests/refdesigns/aws_xrt/vitis_1activator_200_125.awsxclbin index 7b23ab69..2478df7c 100644 Binary files a/tests/refdesigns/aws_xrt/vitis_1activator_200_125.awsxclbin and b/tests/refdesigns/aws_xrt/vitis_1activator_200_125.awsxclbin differ diff --git a/tests/refdesigns/aws_xrt/vitis_1activator_som_125.awsxclbin b/tests/refdesigns/aws_xrt/vitis_1activator_som_125.awsxclbin index e380e035..7f6e76ce 100644 Binary files a/tests/refdesigns/aws_xrt/vitis_1activator_som_125.awsxclbin and b/tests/refdesigns/aws_xrt/vitis_1activator_som_125.awsxclbin differ diff --git a/tests/refdesigns/aws_xrt/vitis_2activator_100_125.awsxclbin b/tests/refdesigns/aws_xrt/vitis_2activator_100_125.awsxclbin index c7ad39ed..d145900a 100644 Binary files a/tests/refdesigns/aws_xrt/vitis_2activator_100_125.awsxclbin and b/tests/refdesigns/aws_xrt/vitis_2activator_100_125.awsxclbin differ diff --git a/tests/refdesigns/aws_xrt/vitis_2activator_125.awsxclbin b/tests/refdesigns/aws_xrt/vitis_2activator_125.awsxclbin index ae70cc13..a2f12d1e 100644 Binary files a/tests/refdesigns/aws_xrt/vitis_2activator_125.awsxclbin and b/tests/refdesigns/aws_xrt/vitis_2activator_125.awsxclbin differ diff --git a/tests/refdesigns/aws_xrt/vitis_2activator_350_350.awsxclbin b/tests/refdesigns/aws_xrt/vitis_2activator_350_350.awsxclbin index 0432997b..2a38e272 100644 Binary files a/tests/refdesigns/aws_xrt/vitis_2activator_350_350.awsxclbin and b/tests/refdesigns/aws_xrt/vitis_2activator_350_350.awsxclbin differ diff --git a/tests/refdesigns/aws_xrt/vitis_2activator_slr_200_125.awsxclbin b/tests/refdesigns/aws_xrt/vitis_2activator_slr_200_125.awsxclbin index 21f6c4f2..9088dbe4 100644 Binary files a/tests/refdesigns/aws_xrt/vitis_2activator_slr_200_125.awsxclbin and b/tests/refdesigns/aws_xrt/vitis_2activator_slr_200_125.awsxclbin differ diff --git a/tests/refdesigns/aws_xrt/vitis_2activator_vhdl_125.awsxclbin b/tests/refdesigns/aws_xrt/vitis_2activator_vhdl_125.awsxclbin index e775e086..1bd103d9 100644 Binary files a/tests/refdesigns/aws_xrt/vitis_2activator_vhdl_125.awsxclbin and b/tests/refdesigns/aws_xrt/vitis_2activator_vhdl_125.awsxclbin differ diff --git a/tests/refdesigns/aws_xrt/vitis_2activator_vhdl_250_125.awsxclbin b/tests/refdesigns/aws_xrt/vitis_2activator_vhdl_250_125.awsxclbin index 0a9c8ffa..92297514 100644 Binary files a/tests/refdesigns/aws_xrt/vitis_2activator_vhdl_250_125.awsxclbin and b/tests/refdesigns/aws_xrt/vitis_2activator_vhdl_250_125.awsxclbin differ diff --git a/tests/test_awsf1_refdesign.py b/tests/test_awsf1_refdesign.py index 0a1685ed..f5fb7c86 100644 --- a/tests/test_awsf1_refdesign.py +++ b/tests/test_awsf1_refdesign.py @@ -115,12 +115,12 @@ def run_test_on_design(accelize_drm, design_name, conf_json, cred_json, async_ha @pytest.mark.awsf1 -def test_1activator_axi4_125(accelize_drm, conf_json, cred_json, async_handler, log_file_factory): +def test_1activator_125(accelize_drm, conf_json, cred_json, async_handler, log_file_factory): """ Test a RTL vivado configuration: 1 single clock kernels with Verilog source """ # Run test - design_name = '1activator_axi4_125' + design_name = '1activator_125' axiclk_freq_ref = 125 drmclk_freq_ref = 125 log_content = run_test_on_design(accelize_drm, design_name, conf_json, cred_json, async_handler, @@ -128,12 +128,12 @@ def test_1activator_axi4_125(accelize_drm, conf_json, cred_json, async_handler, @pytest.mark.awsf1 -def test_2activator_axi4_125(accelize_drm, conf_json, cred_json, async_handler, log_file_factory): +def test_2activator_125(accelize_drm, conf_json, cred_json, async_handler, log_file_factory): """ Test a RTL vivado configuration: single clock kernels with Verilog source """ # Run test - design_name = '2activator_axi4_125' + design_name = '2activator_125' axiclk_freq_ref = 125 drmclk_freq_ref = 125 log_content = run_test_on_design(accelize_drm, design_name, conf_json, cred_json, async_handler, @@ -141,25 +141,25 @@ def test_2activator_axi4_125(accelize_drm, conf_json, cred_json, async_handler, @pytest.mark.awsf1 -def test_2activator_axi4_250_125(accelize_drm, conf_json, cred_json, async_handler, log_file_factory): +def test_2activator_15_125(accelize_drm, conf_json, cred_json, async_handler, log_file_factory): """ Test a RTL vivado configuration: dual clock kernels with Verilog source """ # Run test - design_name = '2activator_axi4_250_125' - axiclk_freq_ref = 250 + design_name = '2activator_15_125' + axiclk_freq_ref = 15 drmclk_freq_ref = 125 log_content = run_test_on_design(accelize_drm, design_name, conf_json, cred_json, async_handler, log_file_factory, axiclk_freq_ref, drmclk_freq_ref) @pytest.mark.awsf1 -def test_2activator_axi4_vhdl_125(accelize_drm, conf_json, cred_json, async_handler, log_file_factory): +def test_2activator_vhdl_125(accelize_drm, conf_json, cred_json, async_handler, log_file_factory): """ Test a RTL vivado configuration: single clock kernels with VHDL source """ # Run test - design_name = '2activator_axi4_vhdl_125' + design_name = '2activator_vhdl_125' axiclk_freq_ref = 125 drmclk_freq_ref = 125 log_content = run_test_on_design(accelize_drm, design_name, conf_json, cred_json, async_handler, @@ -167,28 +167,41 @@ def test_2activator_axi4_vhdl_125(accelize_drm, conf_json, cred_json, async_hand @pytest.mark.awsf1 -def test_2activator_axi4_swap_activator_250_125(accelize_drm, conf_json, cred_json, async_handler, log_file_factory): +def test_2activator_vhdl_15_225(accelize_drm, conf_json, cred_json, async_handler, log_file_factory): + """ + Test a RTL vivado configuration: dual clock kernels with VHDL source + """ + # Run test + design_name = '2activator_vhdl_15_225' + axiclk_freq_ref = 15 + drmclk_freq_ref = 225 + log_content = run_test_on_design(accelize_drm, design_name, conf_json, cred_json, async_handler, + log_file_factory, axiclk_freq_ref, drmclk_freq_ref) + + +@pytest.mark.awsf1 +def test_2activator_250_75_swap_activator(accelize_drm, conf_json, cred_json, async_handler, log_file_factory): """ Test a RTL vivado configuration: dual clock kernels with activators inverted on LGDN bus """ # Run test - design_name = '2activator_axi4_swap_activator_250_125' + design_name = '2activator_250_75_swap_activator' axiclk_freq_ref = 250 - drmclk_freq_ref = 125 + drmclk_freq_ref = 75 log_content = run_test_on_design(accelize_drm, design_name, conf_json, cred_json, async_handler, log_file_factory, axiclk_freq_ref, drmclk_freq_ref) @pytest.mark.skip(reason='To be manually executed: only used to check the behavior of the DRM Controller IP when 1 activator is missing out of 2') @pytest.mark.awsf1 -def test_2activator_2clk_missing_1activator(accelize_drm, conf_json, cred_json, async_handler, log_file_factory): +def test_2activator_missing_1activator(accelize_drm, conf_json, cred_json, async_handler, log_file_factory): """ Test a RTL vivado configuration: dual clock kernels with one missing activator Verify that is works as expected """ # Run test - design_name = '2activator_2clk_missing_1activator' - axiclk_freq_ref = 250 + design_name = '2activator_missing_1activator' + axiclk_freq_ref = 15 drmclk_freq_ref = 125 log_content = run_test_on_design(accelize_drm, design_name, conf_json, cred_json, async_handler, log_file_factory, axiclk_freq_ref, drmclk_freq_ref) diff --git a/tests/test_vitis_refdesign.py b/tests/test_vitis_refdesign.py index 08d49b42..a5c0eeb2 100644 --- a/tests/test_vitis_refdesign.py +++ b/tests/test_vitis_refdesign.py @@ -121,8 +121,8 @@ def test_vitis_1activator_200_125(accelize_drm, conf_json, cred_json, async_hand Test a vitis configuration: 1 activator with dual clock kernels (AXI clock > DRM clock) """ design_name = 'vitis_1activator_200_125' - axiclk_freq_ref = 200 - drmclk_freq_ref = 125 + axiclk_freq_ref = 225 + drmclk_freq_ref = 90 log_content = run_test_on_design(accelize_drm, design_name, conf_json, cred_json, async_handler, log_file_factory, axiclk_freq_ref, drmclk_freq_ref) @@ -146,8 +146,8 @@ def test_vitis_2activator_vhdl_250_125(accelize_drm, conf_json, cred_json, async """ # Run test design_name = 'vitis_2activator_vhdl_250_125' - axiclk_freq_ref = 250 - drmclk_freq_ref = 125 + axiclk_freq_ref = 225 + drmclk_freq_ref = 90 log_content = run_test_on_design(accelize_drm, design_name, conf_json, cred_json, async_handler, log_file_factory, axiclk_freq_ref, drmclk_freq_ref) @@ -172,7 +172,7 @@ def test_vitis_2activator_100_125(accelize_drm, conf_json, cred_json, async_hand """ # Run test design_name = 'vitis_2activator_100_125' - axiclk_freq_ref = 100 + axiclk_freq_ref = 90 drmclk_freq_ref = 125 log_content = run_test_on_design(accelize_drm, design_name, conf_json, cred_json, async_handler, log_file_factory, axiclk_freq_ref, drmclk_freq_ref) @@ -185,8 +185,8 @@ def test_vitis_2activator_slr_200_125(accelize_drm, conf_json, cred_json, async_ """ # Run test design_name = 'vitis_2activator_slr_200_125' - axiclk_freq_ref = 200 - drmclk_freq_ref = 125 + axiclk_freq_ref = 225 + drmclk_freq_ref = 90 log_content = run_test_on_design(accelize_drm, design_name, conf_json, cred_json, async_handler, log_file_factory, axiclk_freq_ref, drmclk_freq_ref) @@ -212,20 +212,20 @@ def test_vitis_2activator_dualclkfifo(accelize_drm, conf_json, cred_json, async_ """ # Run test design_name = 'vitis_2activator_dualclkfifo' - axiclk_freq_ref = 200 - drmclk_freq_ref = 125 + axiclk_freq_ref = 225 + drmclk_freq_ref = 90 log_content = run_test_on_design(accelize_drm, design_name, conf_json, cred_json, async_handler, log_file_factory, axiclk_freq_ref, drmclk_freq_ref) @pytest.mark.skip(reason='No design yet available with 5 activators on high density') @pytest.mark.awsxrt -def test_vitis_5activator_high_density(accelize_drm, conf_json, cred_json, async_handler, log_file_factory): +def test_vitis_5activator_high_density_100_125(accelize_drm, conf_json, cred_json, async_handler, log_file_factory): """ Test a vitis configuration: 5 dual clock activators in a high density design """ # Run test - design_name = 'vitis_5activator_high_density' + design_name = 'vitis_5activator_high_density_100_125' axiclk_freq_ref = 100 drmclk_freq_ref = 125 log_content = run_test_on_design(accelize_drm, design_name, conf_json, cred_json, async_handler, @@ -234,14 +234,14 @@ def test_vitis_5activator_high_density(accelize_drm, conf_json, cred_json, async @pytest.mark.skip(reason='No design yet available with 30 activators') @pytest.mark.awsxrt -def test_vitis_30activator(accelize_drm, conf_json, cred_json, async_handler, log_file_factory): +def test_vitis_30activator_100_125(accelize_drm, conf_json, cred_json, async_handler, log_file_factory): """ Test a vitis configuration: 30 activators """ # Run test - design_name = 'vitis_30activator' - axiclk_freq_ref = 100 - drmclk_freq_ref = 125 + design_name = 'vitis_30activator_100_125' + axiclk_freq_ref = 90 + drmclk_freq_ref = 225 log_content = run_test_on_design(accelize_drm, design_name, conf_json, cred_json, async_handler, log_file_factory, axiclk_freq_ref, drmclk_freq_ref)