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Update mbed hal function as per of SDK update

Signed-off-by: Sadik.Ozer <[email protected]>
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@ozersa
ozersa committed May 17, 2023
1 parent 3f4b177 commit d42b9b3
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Showing 37 changed files with 231 additions and 184 deletions.
6 changes: 2 additions & 4 deletions ...ets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/dma_regs.h
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Expand Up @@ -67,9 +67,7 @@ extern "C" {
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif

/// @endcond

/* **** Definitions **** */
Expand Down Expand Up @@ -99,7 +97,7 @@ typedef struct {
typedef struct {
__IO uint32_t int_en; /**< <tt>\b 0x000:</tt> DMA INT_EN Register */
__I uint32_t int_fl; /**< <tt>\b 0x004:</tt> DMA INT_FL Register */
__R uint32_t rsv_0x8_0xff[62];
__I uint32_t rsv_0x8_0xff[62];
__IO mxc_dma_ch_regs_t ch[4]; /**< <tt>\b 0x100:</tt> DMA CH Register */
} mxc_dma_regs_t;

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4 changes: 1 addition & 3 deletions ...ets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/fcr_regs.h
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Expand Up @@ -67,9 +67,7 @@ extern "C" {
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif

/// @endcond

/* **** Definitions **** */
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8 changes: 3 additions & 5 deletions ...ets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/flc_regs.h
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Expand Up @@ -67,9 +67,7 @@ extern "C" {
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif

/// @endcond

/* **** Definitions **** */
Expand All @@ -89,9 +87,9 @@ typedef struct {
__IO uint32_t addr; /**< <tt>\b 0x00:</tt> FLC ADDR Register */
__IO uint32_t clkdiv; /**< <tt>\b 0x04:</tt> FLC CLKDIV Register */
__IO uint32_t ctrl; /**< <tt>\b 0x08:</tt> FLC CTRL Register */
__R uint32_t rsv_0xc_0x23[6];
__I uint32_t rsv_0xc_0x23[6];
__IO uint32_t intr; /**< <tt>\b 0x024:</tt> FLC INTR Register */
__R uint32_t rsv_0x28_0x2f[2];
__I uint32_t rsv_0x28_0x2f[2];
__IO uint32_t data[4]; /**< <tt>\b 0x30:</tt> FLC DATA Register */
__O uint32_t actrl; /**< <tt>\b 0x40:</tt> FLC ACTRL Register */
} mxc_flc_regs_t;
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8 changes: 3 additions & 5 deletions ...ets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/gcr_regs.h
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Expand Up @@ -67,9 +67,7 @@ extern "C" {
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif

/// @endcond

/* **** Definitions **** */
Expand All @@ -90,11 +88,11 @@ typedef struct {
__IO uint32_t rst0; /**< <tt>\b 0x04:</tt> GCR RST0 Register */
__IO uint32_t clk_ctrl; /**< <tt>\b 0x08:</tt> GCR CLK_CTRL Register */
__IO uint32_t pm; /**< <tt>\b 0x0C:</tt> GCR PM Register */
__R uint32_t rsv_0x10_0x23[5];
__I uint32_t rsv_0x10_0x23[5];
__IO uint32_t pclk_dis0; /**< <tt>\b 0x24:</tt> GCR PCLK_DIS0 Register */
__IO uint32_t mem_ctrl; /**< <tt>\b 0x28:</tt> GCR MEM_CTRL Register */
__IO uint32_t mem_zctrl; /**< <tt>\b 0x2C:</tt> GCR MEM_ZCTRL Register */
__R uint32_t rsv_0x30_0x3f[4];
__I uint32_t rsv_0x30_0x3f[4];
__IO uint32_t sys_stat; /**< <tt>\b 0x40:</tt> GCR SYS_STAT Register */
__IO uint32_t rst1; /**< <tt>\b 0x44:</tt> GCR RST1 Register */
__IO uint32_t pclk_dis1; /**< <tt>\b 0x48:</tt> GCR PCLK_DIS1 Register */
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13 changes: 5 additions & 8 deletions ...ts/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/gpio_regs.h
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Expand Up @@ -67,9 +67,6 @@ extern "C" {
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond

/* **** Definitions **** */
Expand Down Expand Up @@ -102,13 +99,13 @@ typedef struct {
__IO uint32_t int_en; /**< <tt>\b 0x34:</tt> GPIO INT_EN Register */
__IO uint32_t int_en_set; /**< <tt>\b 0x38:</tt> GPIO INT_EN_SET Register */
__IO uint32_t int_en_clr; /**< <tt>\b 0x3C:</tt> GPIO INT_EN_CLR Register */
__I uint32_t int_stat; /**< <tt>\b 0x40:</tt> GPIO INT_STAT Register */
__R uint32_t rsv_0x44;
__IO uint32_t int_stat; /**< <tt>\b 0x40:</tt> GPIO INT_STAT Register */
__I uint32_t rsv_0x44;
__IO uint32_t int_clr; /**< <tt>\b 0x48:</tt> GPIO INT_CLR Register */
__IO uint32_t wake_en; /**< <tt>\b 0x4C:</tt> GPIO WAKE_EN Register */
__IO uint32_t wake_en_set; /**< <tt>\b 0x50:</tt> GPIO WAKE_EN_SET Register */
__IO uint32_t wake_en_clr; /**< <tt>\b 0x54:</tt> GPIO WAKE_EN_CLR Register */
__R uint32_t rsv_0x58;
__I uint32_t rsv_0x58;
__IO uint32_t int_dual_edge; /**< <tt>\b 0x5C:</tt> GPIO INT_DUAL_EDGE Register */
__IO uint32_t pad_cfg1; /**< <tt>\b 0x60:</tt> GPIO PAD_CFG1 Register */
__IO uint32_t pad_cfg2; /**< <tt>\b 0x64:</tt> GPIO PAD_CFG2 Register */
Expand All @@ -118,13 +115,13 @@ typedef struct {
__IO uint32_t en2; /**< <tt>\b 0x74:</tt> GPIO EN2 Register */
__IO uint32_t en2_set; /**< <tt>\b 0x78:</tt> GPIO EN2_SET Register */
__IO uint32_t en2_clr; /**< <tt>\b 0x7C:</tt> GPIO EN2_CLR Register */
__R uint32_t rsv_0x80_0xa7[10];
__I uint32_t rsv_0x80_0xa7[10];
__IO uint32_t is; /**< <tt>\b 0xA8:</tt> GPIO IS Register */
__IO uint32_t sr; /**< <tt>\b 0xAC:</tt> GPIO SR Register */
__IO uint32_t ds0; /**< <tt>\b 0xB0:</tt> GPIO DS0 Register */
__IO uint32_t ds1; /**< <tt>\b 0xB4:</tt> GPIO DS1 Register */
__IO uint32_t ps; /**< <tt>\b 0xB8:</tt> GPIO PS Register */
__R uint32_t rsv_0xbc;
__I uint32_t rsv_0xbc;
__IO uint32_t vssel; /**< <tt>\b 0xC0:</tt> GPIO VSSEL Register */
} mxc_gpio_regs_t;

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4 changes: 1 addition & 3 deletions ...ets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/i2c_regs.h
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Expand Up @@ -67,9 +67,7 @@ extern "C" {
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif

/// @endcond

/* **** Definitions **** */
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8 changes: 3 additions & 5 deletions ...ets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/icc_regs.h
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Original file line number Diff line number Diff line change
Expand Up @@ -67,9 +67,7 @@ extern "C" {
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif

/// @endcond

/* **** Definitions **** */
Expand All @@ -88,9 +86,9 @@ extern "C" {
typedef struct {
__I uint32_t cache_id; /**< <tt>\b 0x0000:</tt> ICC CACHE_ID Register */
__I uint32_t mem_size; /**< <tt>\b 0x0004:</tt> ICC MEM_SIZE Register */
__R uint32_t rsv_0x8_0xff[62];
__I uint32_t rsv_0x8_0xff[62];
__IO uint32_t cache_ctrl; /**< <tt>\b 0x0100:</tt> ICC CACHE_CTRL Register */
__R uint32_t rsv_0x104_0x6ff[383];
__I uint32_t rsv_0x104_0x6ff[383];
__IO uint32_t invalidate; /**< <tt>\b 0x0700:</tt> ICC INVALIDATE Register */
} mxc_icc_regs_t;

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6 changes: 2 additions & 4 deletions .../TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/pwrseq_regs.h
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Expand Up @@ -67,9 +67,7 @@ extern "C" {
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif

/// @endcond

/* **** Definitions **** */
Expand All @@ -89,7 +87,7 @@ typedef struct {
__IO uint32_t lp_ctrl; /**< <tt>\b 0x00:</tt> PWRSEQ LP_CTRL Register */
__IO uint32_t lp_wakefl; /**< <tt>\b 0x04:</tt> PWRSEQ LP_WAKEFL Register */
__IO uint32_t lpwk_en; /**< <tt>\b 0x08:</tt> PWRSEQ LPWK_EN Register */
__R uint32_t rsv_0xc_0x3f[13];
__I uint32_t rsv_0xc_0x3f[13];
__IO uint32_t lpmemsd; /**< <tt>\b 0x40:</tt> PWRSEQ LPMEMSD Register */
} mxc_pwrseq_regs_t;

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6 changes: 2 additions & 4 deletions ...ets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/spi_regs.h
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Expand Up @@ -67,9 +67,7 @@ extern "C" {
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif

/// @endcond

/* **** Definitions **** */
Expand All @@ -92,7 +90,7 @@ typedef struct {
__IO uint32_t ctrl2; /**< <tt>\b 0x0C:</tt> SPI CTRL2 Register */
__IO uint32_t ss_time; /**< <tt>\b 0x10:</tt> SPI SS_TIME Register */
__IO uint32_t clk_cfg; /**< <tt>\b 0x14:</tt> SPI CLK_CFG Register */
__R uint32_t rsv_0x18;
__I uint32_t rsv_0x18;
__IO uint32_t dma; /**< <tt>\b 0x1C:</tt> SPI DMA Register */
__IO uint32_t int_fl; /**< <tt>\b 0x20:</tt> SPI INT_FL Register */
__IO uint32_t int_en; /**< <tt>\b 0x24:</tt> SPI INT_EN Register */
Expand Down
8 changes: 3 additions & 5 deletions .../TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/spimss_regs.h
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Expand Up @@ -67,9 +67,7 @@ extern "C" {
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif

/// @endcond

/* **** Definitions **** */
Expand All @@ -87,11 +85,11 @@ extern "C" {
*/
typedef struct {
__IO uint16_t data; /**< <tt>\b 0x00:</tt> SPIMSS DATA Register */
__R uint16_t rsv_0x2;
__I uint16_t rsv_0x2;
__IO uint32_t ctrl; /**< <tt>\b 0x04:</tt> SPIMSS CTRL Register */
__IO uint32_t int_fl; /**< <tt>\b 0x08:</tt> SPIMSS INT_FL Register */
__IO uint32_t mode; /**< <tt>\b 0x0C:</tt> SPIMSS MODE Register */
__R uint32_t rsv_0x10;
__I uint32_t rsv_0x10;
__IO uint32_t brg; /**< <tt>\b 0x14:</tt> SPIMSS BRG Register */
__IO uint32_t dma; /**< <tt>\b 0x18:</tt> SPIMSS DMA Register */
__IO uint32_t i2s_ctrl; /**< <tt>\b 0x1C:</tt> SPIMSS I2S_CTRL Register */
Expand Down
4 changes: 1 addition & 3 deletions ...ets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/tmr_regs.h
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Expand Up @@ -67,9 +67,7 @@ extern "C" {
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif

/// @endcond

/* **** Definitions **** */
Expand Down
4 changes: 1 addition & 3 deletions ...ts/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/uart_regs.h
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Expand Up @@ -67,9 +67,7 @@ extern "C" {
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif

/// @endcond

/* **** Definitions **** */
Expand Down
4 changes: 1 addition & 3 deletions ...ets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/wdt_regs.h
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Expand Up @@ -67,9 +67,7 @@ extern "C" {
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif

/// @endcond

/* **** Definitions **** */
Expand Down
53 changes: 18 additions & 35 deletions ...RGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Source/system_max32660.c
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Expand Up @@ -46,7 +46,6 @@
#include "wdt_regs.h"
#include "mxc_sys.h"

extern void (*const __isr_vector[])(void);
uint32_t SystemCoreClock = HIRC96_FREQ;

__weak void SystemCoreClockUpdate(void)
Expand Down Expand Up @@ -76,7 +75,7 @@ __weak void SystemCoreClockUpdate(void)
}

// Get the clock divider
div = (MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_PSC) >> MXC_F_GCR_CLK_CTRL_PSC_POS;
div = (MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_CLKSEL) >> MXC_F_GCR_CLK_CTRL_PSC_POS;

SystemCoreClock = base_freq >> div;
}
Expand All @@ -91,7 +90,12 @@ __weak void SystemCoreClockUpdate(void)
*/
__weak int PreInit(void)
{
/* Do nothing */
/* Switch system clock to HIRC, 96 MHz*/
MXC_SYS_Clock_Select(MXC_SYS_CLOCK_HIRC);

/* Enable cache here to reduce boot time */
MXC_ICC_Enable();

return 0;
}

Expand All @@ -102,6 +106,12 @@ __weak int Board_Init(void)
return 0;
}

/* Override this function for early platform initialization */
__weak void low_level_init(void)
{
/* Do nothing */
}

/* This function is called just before control is transferred to main().
*
* You may over-ride this function in your program by defining a custom
Expand All @@ -110,23 +120,16 @@ __weak int Board_Init(void)
*/
__weak void SystemInit(void)
{
/* Configure the interrupt controller to use the application vector table in */
/* the application space */
/* IAR & Keil must set vector table after all memory initialization. */
SCB->VTOR = (uint32_t)__isr_vector;

MXC_WDT0->ctrl &=
~MXC_F_WDT_CTRL_WDT_EN; /* Turn off watchdog. Application can re-enable as needed. */
MXC_WDT0->ctrl &= ~MXC_F_WDT_CTRL_WDT_EN; /* Turn off watchdog. Application can re-enable as needed. */

#if (__FPU_PRESENT == 1)
/* Enable FPU on Cortex-M4, which occupies coprocessor slots 10 & 11 */
/* Grant full access, per "Table B3-24 CPACR bit assignments". */
/* DDI0403D "ARMv7-M Architecture Reference Manual" */
SCB->CPACR |= SCB_CPACR_CP10_Msk | SCB_CPACR_CP11_Msk;
__DSB();
__ISB();

/* Switch system clock to HIRC */
MXC_SYS_Clock_Select(MXC_SYS_CLOCK_HIRC);
#endif

/* Disable clocks to peripherals by default to reduce power */
MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_DMA);
Expand All @@ -140,26 +143,6 @@ __weak void SystemInit(void)
MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR2);
MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2C1);

Board_Init();
}

#if defined(__CC_ARM)
/* Global variable initialization does not occur until post scatterload in Keil tools.*/

/* External function called after our post scatterload function implementation. */
extern void $Super$$__main_after_scatterload(void);

/**
* @brief Initialization function for SystemCoreClock and Board_Init.
* @details $Sub$$__main_after_scatterload is called during system startup in the Keil
* toolset. Global variable and static variable space must be set up by the compiler
* prior to using these memory spaces. Setting up the SystemCoreClock and Board_Init
* require global memory for variable storage and are called from this function in
* the Keil tool chain.
*/
void $Sub$$__main_after_scatterload(void)
{
SystemInit();
$Super$$__main_after_scatterload();
/* Early platform initialization */
low_level_init();
}
#endif /* __CC_ARM */
12 changes: 6 additions & 6 deletions targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/lp.h
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Expand Up @@ -160,18 +160,18 @@ void MXC_LP_DisableSysRAM0LightSleep(void);
* @brief Enables the selected GPIO port and its selected pins to wake up the device from any low power mode.
* Call this function multiple times to enable pins on multiple ports. This function does not configure
* the GPIO pins nor does it setup their interrupt functionality.
* @param wu_pins The port and pins to configure as wakeup sources. Only the gpio and mask fields of the
* structure are used. The func and pad fields are ignored.
* @param port The port to configure as wakeup sources.
* @param mask The pins to configure as wakeup sources.
*/
void MXC_LP_EnableGPIOWakeup(const mxc_gpio_cfg_t *wu_pins);
void MXC_LP_EnableGPIOWakeup(unsigned int port, unsigned int mask);

/**
* @brief Disables the selected GPIO port and its selected pins as a wake up source.
* Call this function multiple times to disable pins on multiple ports.
* @param wu_pins The port and pins to disable as wakeup sources. Only the gpio and mask fields of the
* structure are used. The func and pad fields are ignored.
* @param port The port to configure as wakeup sources.
* @param mask The pins to configure as wakeup sources.
*/
void MXC_LP_DisableGPIOWakeup(const mxc_gpio_cfg_t *wu_pins);
void MXC_LP_DisableGPIOWakeup(unsigned int port, unsigned int mask);

/**
* @brief Enables the RTC alarm to wake up the device from any low power mode.
Expand Down
2 changes: 2 additions & 0 deletions targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_device.h
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Expand Up @@ -49,7 +49,9 @@
// Create a string definition for the TARGET
#define STRING_ARG(arg) #arg
#define STRING_NAME(name) STRING_ARG(name)
#if MBED_VERSION && MBED_VERSION < 51200
#define TARGET_NAME STRING_NAME(TARGET)
#endif

// Define which revisions of the IP we are using
#ifndef TARGET_REV
Expand Down
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