diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/dma_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/dma_regs.h index 8f4eee916555..2b5d236eeb99 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/dma_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/dma_regs.h @@ -67,9 +67,7 @@ extern "C" { #ifndef __O #define __O volatile #endif -#ifndef __R -#define __R volatile const -#endif + /// @endcond /* **** Definitions **** */ @@ -99,7 +97,7 @@ typedef struct { typedef struct { __IO uint32_t int_en; /**< \b 0x000: DMA INT_EN Register */ __I uint32_t int_fl; /**< \b 0x004: DMA INT_FL Register */ - __R uint32_t rsv_0x8_0xff[62]; + __I uint32_t rsv_0x8_0xff[62]; __IO mxc_dma_ch_regs_t ch[4]; /**< \b 0x100: DMA CH Register */ } mxc_dma_regs_t; diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/fcr_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/fcr_regs.h index ff3389c449b9..fdfb8cc23785 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/fcr_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/fcr_regs.h @@ -67,9 +67,7 @@ extern "C" { #ifndef __O #define __O volatile #endif -#ifndef __R -#define __R volatile const -#endif + /// @endcond /* **** Definitions **** */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/flc_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/flc_regs.h index 18d474a74346..931fff37a776 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/flc_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/flc_regs.h @@ -67,9 +67,7 @@ extern "C" { #ifndef __O #define __O volatile #endif -#ifndef __R -#define __R volatile const -#endif + /// @endcond /* **** Definitions **** */ @@ -89,9 +87,9 @@ typedef struct { __IO uint32_t addr; /**< \b 0x00: FLC ADDR Register */ __IO uint32_t clkdiv; /**< \b 0x04: FLC CLKDIV Register */ __IO uint32_t ctrl; /**< \b 0x08: FLC CTRL Register */ - __R uint32_t rsv_0xc_0x23[6]; + __I uint32_t rsv_0xc_0x23[6]; __IO uint32_t intr; /**< \b 0x024: FLC INTR Register */ - __R uint32_t rsv_0x28_0x2f[2]; + __I uint32_t rsv_0x28_0x2f[2]; __IO uint32_t data[4]; /**< \b 0x30: FLC DATA Register */ __O uint32_t actrl; /**< \b 0x40: FLC ACTRL Register */ } mxc_flc_regs_t; diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/gcr_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/gcr_regs.h index d21a6d77a806..2dc5b6ba511b 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/gcr_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/gcr_regs.h @@ -67,9 +67,7 @@ extern "C" { #ifndef __O #define __O volatile #endif -#ifndef __R -#define __R volatile const -#endif + /// @endcond /* **** Definitions **** */ @@ -90,11 +88,11 @@ typedef struct { __IO uint32_t rst0; /**< \b 0x04: GCR RST0 Register */ __IO uint32_t clk_ctrl; /**< \b 0x08: GCR CLK_CTRL Register */ __IO uint32_t pm; /**< \b 0x0C: GCR PM Register */ - __R uint32_t rsv_0x10_0x23[5]; + __I uint32_t rsv_0x10_0x23[5]; __IO uint32_t pclk_dis0; /**< \b 0x24: GCR PCLK_DIS0 Register */ __IO uint32_t mem_ctrl; /**< \b 0x28: GCR MEM_CTRL Register */ __IO uint32_t mem_zctrl; /**< \b 0x2C: GCR MEM_ZCTRL Register */ - __R uint32_t rsv_0x30_0x3f[4]; + __I uint32_t rsv_0x30_0x3f[4]; __IO uint32_t sys_stat; /**< \b 0x40: GCR SYS_STAT Register */ __IO uint32_t rst1; /**< \b 0x44: GCR RST1 Register */ __IO uint32_t pclk_dis1; /**< \b 0x48: GCR PCLK_DIS1 Register */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/gpio_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/gpio_regs.h index f791e4cfd437..96613b6313a9 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/gpio_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/gpio_regs.h @@ -67,9 +67,6 @@ extern "C" { #ifndef __O #define __O volatile #endif -#ifndef __R -#define __R volatile const -#endif /// @endcond /* **** Definitions **** */ @@ -102,13 +99,13 @@ typedef struct { __IO uint32_t int_en; /**< \b 0x34: GPIO INT_EN Register */ __IO uint32_t int_en_set; /**< \b 0x38: GPIO INT_EN_SET Register */ __IO uint32_t int_en_clr; /**< \b 0x3C: GPIO INT_EN_CLR Register */ - __I uint32_t int_stat; /**< \b 0x40: GPIO INT_STAT Register */ - __R uint32_t rsv_0x44; + __IO uint32_t int_stat; /**< \b 0x40: GPIO INT_STAT Register */ + __I uint32_t rsv_0x44; __IO uint32_t int_clr; /**< \b 0x48: GPIO INT_CLR Register */ __IO uint32_t wake_en; /**< \b 0x4C: GPIO WAKE_EN Register */ __IO uint32_t wake_en_set; /**< \b 0x50: GPIO WAKE_EN_SET Register */ __IO uint32_t wake_en_clr; /**< \b 0x54: GPIO WAKE_EN_CLR Register */ - __R uint32_t rsv_0x58; + __I uint32_t rsv_0x58; __IO uint32_t int_dual_edge; /**< \b 0x5C: GPIO INT_DUAL_EDGE Register */ __IO uint32_t pad_cfg1; /**< \b 0x60: GPIO PAD_CFG1 Register */ __IO uint32_t pad_cfg2; /**< \b 0x64: GPIO PAD_CFG2 Register */ @@ -118,13 +115,13 @@ typedef struct { __IO uint32_t en2; /**< \b 0x74: GPIO EN2 Register */ __IO uint32_t en2_set; /**< \b 0x78: GPIO EN2_SET Register */ __IO uint32_t en2_clr; /**< \b 0x7C: GPIO EN2_CLR Register */ - __R uint32_t rsv_0x80_0xa7[10]; + __I uint32_t rsv_0x80_0xa7[10]; __IO uint32_t is; /**< \b 0xA8: GPIO IS Register */ __IO uint32_t sr; /**< \b 0xAC: GPIO SR Register */ __IO uint32_t ds0; /**< \b 0xB0: GPIO DS0 Register */ __IO uint32_t ds1; /**< \b 0xB4: GPIO DS1 Register */ __IO uint32_t ps; /**< \b 0xB8: GPIO PS Register */ - __R uint32_t rsv_0xbc; + __I uint32_t rsv_0xbc; __IO uint32_t vssel; /**< \b 0xC0: GPIO VSSEL Register */ } mxc_gpio_regs_t; diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/i2c_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/i2c_regs.h index d370b74064df..d713e4d4e5c0 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/i2c_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/i2c_regs.h @@ -67,9 +67,7 @@ extern "C" { #ifndef __O #define __O volatile #endif -#ifndef __R -#define __R volatile const -#endif + /// @endcond /* **** Definitions **** */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/icc_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/icc_regs.h index 3ef38ffa9690..2dc1b58136e2 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/icc_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/icc_regs.h @@ -67,9 +67,7 @@ extern "C" { #ifndef __O #define __O volatile #endif -#ifndef __R -#define __R volatile const -#endif + /// @endcond /* **** Definitions **** */ @@ -88,9 +86,9 @@ extern "C" { typedef struct { __I uint32_t cache_id; /**< \b 0x0000: ICC CACHE_ID Register */ __I uint32_t mem_size; /**< \b 0x0004: ICC MEM_SIZE Register */ - __R uint32_t rsv_0x8_0xff[62]; + __I uint32_t rsv_0x8_0xff[62]; __IO uint32_t cache_ctrl; /**< \b 0x0100: ICC CACHE_CTRL Register */ - __R uint32_t rsv_0x104_0x6ff[383]; + __I uint32_t rsv_0x104_0x6ff[383]; __IO uint32_t invalidate; /**< \b 0x0700: ICC INVALIDATE Register */ } mxc_icc_regs_t; diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/pwrseq_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/pwrseq_regs.h index 95dbebaa069b..3d9ca43447e0 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/pwrseq_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/pwrseq_regs.h @@ -67,9 +67,7 @@ extern "C" { #ifndef __O #define __O volatile #endif -#ifndef __R -#define __R volatile const -#endif + /// @endcond /* **** Definitions **** */ @@ -89,7 +87,7 @@ typedef struct { __IO uint32_t lp_ctrl; /**< \b 0x00: PWRSEQ LP_CTRL Register */ __IO uint32_t lp_wakefl; /**< \b 0x04: PWRSEQ LP_WAKEFL Register */ __IO uint32_t lpwk_en; /**< \b 0x08: PWRSEQ LPWK_EN Register */ - __R uint32_t rsv_0xc_0x3f[13]; + __I uint32_t rsv_0xc_0x3f[13]; __IO uint32_t lpmemsd; /**< \b 0x40: PWRSEQ LPMEMSD Register */ } mxc_pwrseq_regs_t; diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/spi_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/spi_regs.h index 35f8aec98425..759cbe94450f 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/spi_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/spi_regs.h @@ -67,9 +67,7 @@ extern "C" { #ifndef __O #define __O volatile #endif -#ifndef __R -#define __R volatile const -#endif + /// @endcond /* **** Definitions **** */ @@ -92,7 +90,7 @@ typedef struct { __IO uint32_t ctrl2; /**< \b 0x0C: SPI CTRL2 Register */ __IO uint32_t ss_time; /**< \b 0x10: SPI SS_TIME Register */ __IO uint32_t clk_cfg; /**< \b 0x14: SPI CLK_CFG Register */ - __R uint32_t rsv_0x18; + __I uint32_t rsv_0x18; __IO uint32_t dma; /**< \b 0x1C: SPI DMA Register */ __IO uint32_t int_fl; /**< \b 0x20: SPI INT_FL Register */ __IO uint32_t int_en; /**< \b 0x24: SPI INT_EN Register */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/spimss_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/spimss_regs.h index d5638e3e6edf..53e7b1fd3b22 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/spimss_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/spimss_regs.h @@ -67,9 +67,7 @@ extern "C" { #ifndef __O #define __O volatile #endif -#ifndef __R -#define __R volatile const -#endif + /// @endcond /* **** Definitions **** */ @@ -87,11 +85,11 @@ extern "C" { */ typedef struct { __IO uint16_t data; /**< \b 0x00: SPIMSS DATA Register */ - __R uint16_t rsv_0x2; + __I uint16_t rsv_0x2; __IO uint32_t ctrl; /**< \b 0x04: SPIMSS CTRL Register */ __IO uint32_t int_fl; /**< \b 0x08: SPIMSS INT_FL Register */ __IO uint32_t mode; /**< \b 0x0C: SPIMSS MODE Register */ - __R uint32_t rsv_0x10; + __I uint32_t rsv_0x10; __IO uint32_t brg; /**< \b 0x14: SPIMSS BRG Register */ __IO uint32_t dma; /**< \b 0x18: SPIMSS DMA Register */ __IO uint32_t i2s_ctrl; /**< \b 0x1C: SPIMSS I2S_CTRL Register */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/tmr_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/tmr_regs.h index b1073ea226b4..bca94126c7aa 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/tmr_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/tmr_regs.h @@ -67,9 +67,7 @@ extern "C" { #ifndef __O #define __O volatile #endif -#ifndef __R -#define __R volatile const -#endif + /// @endcond /* **** Definitions **** */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/uart_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/uart_regs.h index 6eeec71d0868..cad0f3409b30 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/uart_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/uart_regs.h @@ -67,9 +67,7 @@ extern "C" { #ifndef __O #define __O volatile #endif -#ifndef __R -#define __R volatile const -#endif + /// @endcond /* **** Definitions **** */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/wdt_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/wdt_regs.h index 67f72795be20..d1f414711a25 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/wdt_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/wdt_regs.h @@ -67,9 +67,7 @@ extern "C" { #ifndef __O #define __O volatile #endif -#ifndef __R -#define __R volatile const -#endif + /// @endcond /* **** Definitions **** */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Source/system_max32660.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Source/system_max32660.c index 3565907b90f0..e4db445ea6d5 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Source/system_max32660.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Source/system_max32660.c @@ -46,7 +46,6 @@ #include "wdt_regs.h" #include "mxc_sys.h" -extern void (*const __isr_vector[])(void); uint32_t SystemCoreClock = HIRC96_FREQ; __weak void SystemCoreClockUpdate(void) @@ -76,7 +75,7 @@ __weak void SystemCoreClockUpdate(void) } // Get the clock divider - div = (MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_PSC) >> MXC_F_GCR_CLK_CTRL_PSC_POS; + div = (MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_CLKSEL) >> MXC_F_GCR_CLK_CTRL_PSC_POS; SystemCoreClock = base_freq >> div; } @@ -91,7 +90,12 @@ __weak void SystemCoreClockUpdate(void) */ __weak int PreInit(void) { - /* Do nothing */ + /* Switch system clock to HIRC, 96 MHz*/ + MXC_SYS_Clock_Select(MXC_SYS_CLOCK_HIRC); + + /* Enable cache here to reduce boot time */ + MXC_ICC_Enable(); + return 0; } @@ -102,6 +106,12 @@ __weak int Board_Init(void) return 0; } +/* Override this function for early platform initialization */ +__weak void low_level_init(void) +{ + /* Do nothing */ +} + /* This function is called just before control is transferred to main(). * * You may over-ride this function in your program by defining a custom @@ -110,23 +120,16 @@ __weak int Board_Init(void) */ __weak void SystemInit(void) { - /* Configure the interrupt controller to use the application vector table in */ - /* the application space */ - /* IAR & Keil must set vector table after all memory initialization. */ - SCB->VTOR = (uint32_t)__isr_vector; - - MXC_WDT0->ctrl &= - ~MXC_F_WDT_CTRL_WDT_EN; /* Turn off watchdog. Application can re-enable as needed. */ + MXC_WDT0->ctrl &= ~MXC_F_WDT_CTRL_WDT_EN; /* Turn off watchdog. Application can re-enable as needed. */ +#if (__FPU_PRESENT == 1) /* Enable FPU on Cortex-M4, which occupies coprocessor slots 10 & 11 */ /* Grant full access, per "Table B3-24 CPACR bit assignments". */ /* DDI0403D "ARMv7-M Architecture Reference Manual" */ SCB->CPACR |= SCB_CPACR_CP10_Msk | SCB_CPACR_CP11_Msk; __DSB(); __ISB(); - - /* Switch system clock to HIRC */ - MXC_SYS_Clock_Select(MXC_SYS_CLOCK_HIRC); +#endif /* Disable clocks to peripherals by default to reduce power */ MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_DMA); @@ -140,26 +143,6 @@ __weak void SystemInit(void) MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR2); MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2C1); - Board_Init(); -} - -#if defined(__CC_ARM) -/* Global variable initialization does not occur until post scatterload in Keil tools.*/ - -/* External function called after our post scatterload function implementation. */ -extern void $Super$$__main_after_scatterload(void); - -/** - * @brief Initialization function for SystemCoreClock and Board_Init. - * @details $Sub$$__main_after_scatterload is called during system startup in the Keil - * toolset. Global variable and static variable space must be set up by the compiler - * prior to using these memory spaces. Setting up the SystemCoreClock and Board_Init - * require global memory for variable storage and are called from this function in - * the Keil tool chain. - */ -void $Sub$$__main_after_scatterload(void) -{ - SystemInit(); - $Super$$__main_after_scatterload(); + /* Early platform initialization */ + low_level_init(); } -#endif /* __CC_ARM */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/lp.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/lp.h index a92e07b9bd47..d47f2bade87d 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/lp.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/lp.h @@ -160,18 +160,18 @@ void MXC_LP_DisableSysRAM0LightSleep(void); * @brief Enables the selected GPIO port and its selected pins to wake up the device from any low power mode. * Call this function multiple times to enable pins on multiple ports. This function does not configure * the GPIO pins nor does it setup their interrupt functionality. - * @param wu_pins The port and pins to configure as wakeup sources. Only the gpio and mask fields of the - * structure are used. The func and pad fields are ignored. + * @param port The port to configure as wakeup sources. + * @param mask The pins to configure as wakeup sources. */ -void MXC_LP_EnableGPIOWakeup(const mxc_gpio_cfg_t *wu_pins); +void MXC_LP_EnableGPIOWakeup(unsigned int port, unsigned int mask); /** * @brief Disables the selected GPIO port and its selected pins as a wake up source. * Call this function multiple times to disable pins on multiple ports. - * @param wu_pins The port and pins to disable as wakeup sources. Only the gpio and mask fields of the - * structure are used. The func and pad fields are ignored. + * @param port The port to configure as wakeup sources. + * @param mask The pins to configure as wakeup sources. */ -void MXC_LP_DisableGPIOWakeup(const mxc_gpio_cfg_t *wu_pins); +void MXC_LP_DisableGPIOWakeup(unsigned int port, unsigned int mask); /** * @brief Enables the RTC alarm to wake up the device from any low power mode. diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_device.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_device.h index 5d80f0c3599a..b652db2c67d7 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_device.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_device.h @@ -49,7 +49,9 @@ // Create a string definition for the TARGET #define STRING_ARG(arg) #arg #define STRING_NAME(name) STRING_ARG(name) +#if MBED_VERSION && MBED_VERSION < 51200 #define TARGET_NAME STRING_NAME(TARGET) +#endif // Define which revisions of the IP we are using #ifndef TARGET_REV diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_lock.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_lock.h index cd91bcd2b1bf..450ea27a5816 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_lock.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_lock.h @@ -40,6 +40,9 @@ #ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_LOCK_H_ #define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_LOCK_H_ +// To enable disable this module +#define USE_LOCK_IN_DRIVERS 0 + /* **** Includes **** */ #include "mxc_device.h" @@ -47,6 +50,8 @@ extern "C" { #endif +#if USE_LOCK_IN_DRIVERS + /** * @ingroup syscfg * @defgroup mxc_lock_utilities Exclusive Access Locks @@ -88,4 +93,11 @@ void MXC_FreeLock(uint32_t *lock); } #endif +#else // USE_LOCK_IN_DRIVERS + +#define MXC_GetLock(x, y) E_NO_ERROR +#define MXC_FreeLock(x) + +#endif // USE_LOCK_IN_DRIVERS + #endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_LOCK_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_pins.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_pins.h index 1d28443610cc..f7e4e654b36e 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_pins.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_pins.h @@ -60,8 +60,11 @@ extern const mxc_gpio_cfg_t gpio_cfg_uart1c; extern const mxc_gpio_cfg_t gpio_cfg_uart1_flow; extern const mxc_gpio_cfg_t gpio_cfg_spi0; +extern const mxc_gpio_cfg_t gpio_cfg_spi0_ss; extern const mxc_gpio_cfg_t gpio_cfg_spi1a; +extern const mxc_gpio_cfg_t gpio_cfg_spi1a_ss; extern const mxc_gpio_cfg_t gpio_cfg_spi1b; +extern const mxc_gpio_cfg_t gpio_cfg_spi1b_ss; // Timers are only defined once, depending on package, each timer could be mapped to other pins extern const mxc_gpio_cfg_t gpio_cfg_tmr0; diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_spi.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_spi.h index 6121e44de9e7..8090125c17fa 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_spi.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_spi.h @@ -169,12 +169,14 @@ struct _mxc_spi_req_t { * @param hz The requested clock frequency. The actual clock frequency * will be returned by the function if successful. Used in * master mode only. - * + * @param drv_ssel Hardware block able to drive SS pin, or it can be leaved as it is + * To upper layer firmware drive it. + * 1:Driver will drive SS pin, 0:Driver will NOT drive it * @return If successful, the actual clock frequency is returned. Otherwise, see * \ref MXC_Error_Codes for a list of return codes. */ int MXC_SPI_Init(mxc_spi_regs_t *spi, int masterMode, int quadModeUsed, int numSlaves, - unsigned ssPolarity, unsigned int hz); + unsigned ssPolarity, unsigned int hz, unsigned drv_ssel); /** * @brief Disable and shutdown SPI peripheral. diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_sys.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_sys.h index b33976271ecf..57b3dff9c481 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_sys.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_sys.h @@ -122,7 +122,7 @@ typedef struct { int in_critical; } mxc_crit_state_t; -static mxc_crit_state_t _state = { .ie_status = 0xFFFFFFFF, .in_critical = 0 }; +static mxc_crit_state_t _state = { .ie_status = (int)0xFFFFFFFF, .in_critical = 0 }; static inline void _mxc_crit_get_state() { diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/spimss.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/spimss.h index e5df3e13a7b0..86637941c37f 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/spimss.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/spimss.h @@ -116,7 +116,7 @@ struct mxc_spimss_req { * * @return \c #E_NO_ERROR if successful, appropriate error otherwise */ -int MXC_SPIMSS_Init(mxc_spimss_regs_t *spi, unsigned mode, unsigned freq, const sys_map_t sys_cfg); +int MXC_SPIMSS_Init(mxc_spimss_regs_t *spi, unsigned mode, unsigned freq, const sys_map_t sys_cfg, unsigned drv_ssel); /** * @brief Shutdown SPI module. @@ -175,6 +175,19 @@ int MXC_SPIMSS_MasterTransAsync(mxc_spimss_regs_t *spi, mxc_spimss_req_t *req); */ int MXC_SPIMSS_SlaveTransAsync(mxc_spimss_regs_t *spi, mxc_spimss_req_t *req); +/** + * @brief Sets the TX data to transmit as a 'dummy' byte + * + * In single wire master mode, this data is transmitted on MOSI when performing + * an RX (MISO) only transaction. This defaults to 0. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param defaultTXData Data to shift out in RX-only transactions + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPIMSS_SetDefaultTXData (mxc_spimss_req_t* spi, unsigned int defaultTXData); + /** * @brief Aborts an Asynchronous request * diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/tmr.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/tmr.h index 3ce9bf91b615..cf9d5a0f2676 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/tmr.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/tmr.h @@ -115,12 +115,25 @@ typedef enum { TMR_UNIT_SEC, ///< Second Unit Indicator } mxc_tmr_unit_t; +/** + * @brief Clock settings + * @note 8M and 32M clocks can be used for Timers 0,1,2 and 3 + * 32K and 80K clocks can only be used for Timers 4 and 5 + */ +typedef enum { + MXC_TMR_HFIO_CLK, ///< HFIO Clock + MXC_TMR_NANORING_CLK, ///< 8KHz Nanoring Clock + MXC_TMR_EXT_CLK, ///< External Clock +} mxc_tmr_clock_t; + /** * @brief Timer Configuration */ typedef struct { mxc_tmr_pres_t pres; ///< Desired timer prescaler mxc_tmr_mode_t mode; ///< Desired timer mode + mxc_tmr_bit_mode_t bitMode; ///< Desired timer bits + mxc_tmr_clock_t clock; ///< Desired clock source uint32_t cmp_cnt; ///< Compare register value in timer ticks unsigned pol; ///< Polarity (0 or 1) } mxc_tmr_cfg_t; diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_me11.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_me11.c index bb79c1c2b884..89f8b7e76663 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_me11.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_me11.c @@ -70,11 +70,11 @@ void MXC_FLC_ME11_Flash_Operation(void) // Clear the line fill buffer by reading 2 pages from flash volatile uint32_t *line_addr; - volatile uint32_t __unused line; // __unused attribute removes warning - line_addr = (uint32_t *)(MXC_FLASH_MEM_BASE); - line = *line_addr; + volatile uint32_t line; // __unused attribute removes warning line_addr = (uint32_t *)(MXC_FLASH_MEM_BASE + MXC_FLASH_PAGE_SIZE); line = *line_addr; + line_addr = (uint32_t *)(MXC_FLASH_MEM_BASE + (2 * MXC_FLASH_PAGE_SIZE)); + line = *line_addr; } //****************************************************************************** diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_me11.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_me11.c index ffb3dcfb0b5e..113988d48b84 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_me11.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_me11.c @@ -42,7 +42,7 @@ #include "mxc_delay.h" #include "i2c_regs.h" #include "dma_regs.h" -#include "i2c.h" +#include "mxc_i2c.h" #include "i2c_reva.h" /* **** Definitions **** */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva.c index a9bd8110da97..f6f7fed0567a 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva.c @@ -40,7 +40,7 @@ #include "mxc_sys.h" #include "mxc_delay.h" #include "i2c_regs.h" -#include "i2c.h" +#include "mxc_i2c.h" #include "i2c_reva.h" #include "dma.h" diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/LP/lp_me11.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/LP/lp_me11.c index 5f0514de2ae1..0082a4493412 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/LP/lp_me11.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/LP/lp_me11.c @@ -156,23 +156,24 @@ void MXC_LP_DisableRTCAlarmWakeup(void) MXC_GCR->pm &= ~MXC_F_GCR_PM_RTCWK_EN; } -void MXC_LP_EnableGPIOWakeup(const mxc_gpio_cfg_t *wu_pins) +void MXC_LP_EnableGPIOWakeup(unsigned int port, unsigned int mask) { MXC_GCR->pm |= MXC_F_GCR_PM_GPIOWK_EN; - //switch(wu_pins->port) + //switch(port) //{ - /*case 0:*/ MXC_PWRSEQ->lpwk_en |= wu_pins->mask; //break; + /*case 0:*/ MXC_PWRSEQ->lpwk_en |= mask; //break; //} } -void MXC_LP_DisableGPIOWakeup(const mxc_gpio_cfg_t *wu_pins) +void MXC_LP_DisableGPIOWakeup(unsigned int port, unsigned int mask) { - //switch(wu_pins->port) + //switch(port) //{ - /* case 0:*/ MXC_PWRSEQ->lpwk_en &= ~wu_pins->mask; //break; + /* case 0:*/ MXC_PWRSEQ->lpwk_en &= ~mask; //break; //} - - if (MXC_PWRSEQ->lpwk_en == 0) { + + if(MXC_PWRSEQ->lpwk_en == 0) + { MXC_GCR->pm &= ~MXC_F_GCR_PM_GPIOWK_EN; } } diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_me11.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_me11.c index 00ac830cf372..1177229102e2 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_me11.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_me11.c @@ -44,7 +44,7 @@ /* **** Functions **** */ int MXC_SPI_Init(mxc_spi_regs_t *spi, int masterMode, int quadModeUsed, int numSlaves, - unsigned ssPolarity, unsigned int hz) + unsigned ssPolarity, unsigned int hz, unsigned int drv_ssel) { int spi_num; @@ -71,7 +71,7 @@ int MXC_SPI_Init(mxc_spi_regs_t *spi, int masterMode, int quadModeUsed, int numS } return MXC_SPI_RevA_Init((mxc_spi_reva_regs_t *)spi, masterMode, quadModeUsed, numSlaves, - ssPolarity, hz); + ssPolarity, hz, drv_ssel); } int MXC_SPI_Shutdown(mxc_spi_regs_t *spi) diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva.c index c7a9667341c1..82a54ee24477 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva.c @@ -40,7 +40,7 @@ #include "mxc_lock.h" #include "mxc_sys.h" #include "mxc_delay.h" -#include "spi.h" +#include "mxc_spi.h" #include "spi_reva.h" #include "dma_reva.h" @@ -58,6 +58,7 @@ typedef struct { bool txrx_req; uint8_t req_done; uint8_t async; + unsigned drv_ssel; } spi_req_reva_state_t; static spi_req_reva_state_t states[MXC_SPI_INSTANCES]; @@ -69,7 +70,7 @@ static void MXC_SPI_RevA_SwapByte(uint8_t *arr, size_t length); static int MXC_SPI_RevA_TransSetup(mxc_spi_reva_req_t *req); int MXC_SPI_RevA_Init(mxc_spi_reva_regs_t *spi, int masterMode, int quadModeUsed, int numSlaves, - unsigned ssPolarity, unsigned int hz) + unsigned ssPolarity, unsigned int hz, unsigned int drv_ssel) { int spi_num; @@ -84,6 +85,7 @@ int MXC_SPI_RevA_Init(mxc_spi_reva_regs_t *spi, int masterMode, int quadModeUsed states[spi_num].mtFirstTrans = 0; states[spi_num].channelTx = E_NO_DEVICE; states[spi_num].channelRx = E_NO_DEVICE; + states[spi_num].drv_ssel = drv_ssel; spi->ctrl0 = (MXC_F_SPI_REVA_CTRL0_EN); spi->sstime = @@ -109,22 +111,25 @@ int MXC_SPI_RevA_Init(mxc_spi_reva_regs_t *spi, int masterMode, int quadModeUsed // Clear the interrupts spi->intfl = spi->intfl; - if (numSlaves == 1) { - spi->ctrl0 |= MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0; - } + // Driver will drive SS pin? + if (states[spi_num].drv_ssel) { + if (numSlaves == 1) { + spi->ctrl0 |= MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0; + } - if (numSlaves == 2) { - spi->ctrl0 |= (MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS1); - } + else if (numSlaves == 2) { + spi->ctrl0 |= (MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS1); + } - if (numSlaves == 3) { - spi->ctrl0 |= (MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS1 | - MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS2); - } + else if (numSlaves == 3) { + spi->ctrl0 |= (MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS1 | + MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS2); + } - if (numSlaves == 4) { - spi->ctrl0 |= (MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS1 | - MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS2 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS3); + else if (numSlaves == 4) { + spi->ctrl0 |= (MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS1 | + MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS2 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS3); + } } //set quad mode @@ -364,12 +369,14 @@ int MXC_SPI_RevA_SetSlave(mxc_spi_reva_regs_t *spi, int ssIdx) MXC_ASSERT(spi_num >= 0); (void)spi_num; - // Setup the slave select - // Activate chosen SS pin - spi->ctrl0 |= (1 << ssIdx) << MXC_F_SPI_REVA_CTRL0_SS_ACTIVE_POS; - // Deactivate all unchosen pins - spi->ctrl0 &= ~MXC_F_SPI_REVA_CTRL0_SS_ACTIVE | - ((1 << ssIdx) << MXC_F_SPI_REVA_CTRL0_SS_ACTIVE_POS); + if (states[spi_num].drv_ssel) { + // Setup the slave select + // Activate chosen SS pin + spi->ctrl0 |= (1 << ssIdx) << MXC_F_SPI_REVA_CTRL0_SS_ACTIVE_POS; + // Deactivate all unchosen pins + spi->ctrl0 &= ~MXC_F_SPI_REVA_CTRL0_SS_ACTIVE | + ((1 << ssIdx) << MXC_F_SPI_REVA_CTRL0_SS_ACTIVE_POS); + } return E_NO_ERROR; } @@ -823,8 +830,10 @@ uint32_t MXC_SPI_RevA_MasterTransHandler(mxc_spi_reva_regs_t *spi, mxc_spi_reva_ spi_num = MXC_SPI_GET_IDX((mxc_spi_regs_t *)spi); // Leave slave select asserted at the end of the transaction - if (!req->ssDeassert) { - spi->ctrl0 |= MXC_F_SPI_REVA_CTRL0_SS_CTRL; + if (states[spi_num].drv_ssel) { + if (!req->ssDeassert) { + spi->ctrl0 |= MXC_F_SPI_REVA_CTRL0_SS_CTRL; + } } retval = MXC_SPI_RevA_TransHandler(spi, req); @@ -835,8 +844,10 @@ uint32_t MXC_SPI_RevA_MasterTransHandler(mxc_spi_reva_regs_t *spi, mxc_spi_reva_ } // Deassert slave select at the end of the transaction - if (req->ssDeassert) { - spi->ctrl0 &= ~MXC_F_SPI_REVA_CTRL0_SS_CTRL; + if (states[spi_num].drv_ssel) { + if (req->ssDeassert) { + spi->ctrl0 &= ~MXC_F_SPI_REVA_CTRL0_SS_CTRL; + } } return retval; diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva.h index bfc190d66ad0..6f46c8562d69 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva.h @@ -44,7 +44,7 @@ #include "mxc_delay.h" #include "spi_regs.h" #include "spi_reva_regs.h" -#include "spi.h" +#include "mxc_spi.h" #include "dma.h" #ifdef __cplusplus @@ -81,7 +81,7 @@ struct _mxc_spi_reva_req_t { }; int MXC_SPI_RevA_Init(mxc_spi_reva_regs_t *spi, int masterMode, int quadModeUsed, int numSlaves, - unsigned ssPolarity, unsigned int hz); + unsigned ssPolarity, unsigned int hz, unsigned int drv_ssel); int MXC_SPI_RevA_Shutdown(mxc_spi_reva_regs_t *spi); int MXC_SPI_RevA_ReadyForSleep(mxc_spi_reva_regs_t *spi); int MXC_SPI_RevA_SetFrequency(mxc_spi_reva_regs_t *spi, unsigned int hz); diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_me11.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_me11.c index cf7adfe1cf22..ea47b23dfc2e 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_me11.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_me11.c @@ -45,7 +45,7 @@ /* **** Functions **** */ /* ************************************************************************** */ -int MXC_SPIMSS_Init(mxc_spimss_regs_t *spi, unsigned mode, unsigned freq, const sys_map_t sys_cfg) +int MXC_SPIMSS_Init(mxc_spimss_regs_t *spi, unsigned mode, unsigned freq, const sys_map_t sys_cfg, unsigned drv_ssel) { int spi_num; @@ -78,7 +78,7 @@ int MXC_SPIMSS_Init(mxc_spimss_regs_t *spi, unsigned mode, unsigned freq, const return E_NO_DEVICE; } - return MXC_SPIMSS_RevA_Init((mxc_spimss_reva_regs_t *)spi, mode, freq); + return MXC_SPIMSS_RevA_Init((mxc_spimss_reva_regs_t *)spi, mode, freq, drv_ssel); } /* ************************************************************************* */ int MXC_SPIMSS_Shutdown(mxc_spimss_regs_t *spi) @@ -124,6 +124,13 @@ int MXC_SPIMSS_SlaveTransAsync(mxc_spimss_regs_t *spi, mxc_spimss_req_t *req) { return MXC_SPIMSS_RevA_SlaveTransAsync((mxc_spimss_reva_regs_t *)spi, (spimss_reva_req_t *)req); } + +/* ************************************************************************* */ +int MXC_SPIMSS_SetDefaultTXData(mxc_spimss_req_t* spi, unsigned int defaultTXData) +{ + return MXC_SPIMSS_RevA_SetDefaultTXData((spimss_reva_req_t*) spi, defaultTXData); +} + /* ************************************************************************* */ int MXC_SPIMSS_AbortAsync(mxc_spimss_req_t *req) { diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_reva.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_reva.c index b58537356e64..241fe1719543 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_reva.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_reva.c @@ -57,6 +57,8 @@ /* **** Globals **** */ typedef struct { spimss_reva_req_t *req; + unsigned defaultTXData; + unsigned drv_ssel; } spimss_reva_req_state_t; static spimss_reva_req_state_t states[MXC_SPIMSS_INSTANCES]; @@ -71,7 +73,7 @@ static uint32_t MXC_SPIMSS_RevA_SlaveTransHandler(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req); /* ************************************************************************** */ -int MXC_SPIMSS_RevA_Init(mxc_spimss_reva_regs_t *spi, unsigned mode, unsigned freq) +int MXC_SPIMSS_RevA_Init(mxc_spimss_reva_regs_t *spi, unsigned mode, unsigned freq, unsigned drv_ssel) { int spi_num; unsigned int spimss_clk; @@ -79,6 +81,8 @@ int MXC_SPIMSS_RevA_Init(mxc_spimss_reva_regs_t *spi, unsigned mode, unsigned fr spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t *)spi); states[spi_num].req = NULL; + states[spi_num].defaultTXData = 0; + states[spi_num].drv_ssel = drv_ssel; spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_ENABLE); // Keep the SPI Disabled (This is the SPI Start) // Set the bit rate @@ -164,10 +168,12 @@ int MXC_SPIMSS_RevA_TransSetup(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *r if (master) { // Enable master mode spi->ctrl |= MXC_F_SPIMSS_REVA_CTRL_MMEN; // SPI configured as master. - spi->mode |= MXC_F_SPIMSS_REVA_CTRL_MMEN; // SSEL pin is an output. + if (states[spi_num].drv_ssel) { + spi->mode |= MXC_F_SPIMSS_REVA_MODE_SS_IO; // SSEL pin is an output. + } } else { // Enable slave mode spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_MMEN); // SPI configured as slave. - spi->mode &= ~(MXC_F_SPIMSS_REVA_CTRL_MMEN); // SSEL pin is an input. + spi->mode &= ~(MXC_F_SPIMSS_REVA_MODE_SS_IO); // SSEL pin is an input. } // Setup the character size @@ -180,14 +186,22 @@ int MXC_SPIMSS_RevA_TransSetup(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *r MXC_SETFIELD(spi->mode, MXC_F_SPIMSS_REVA_MODE_NUMBITS, 0 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS); } - - // Setup the slave select - spi->mode |= MXC_F_SPIMSS_REVA_MODE_SSV; // Assert a high on Slave Select, - // to get the line ready for active low later + + if (req->tx_data == NULL) { + // Must have something to send, so we'll use the rx_data buffer initialized to 0. + memset(req->rx_data, states[spi_num].defaultTXData, (req->bits > 8 ? req->len << 1 : req->len)); + req->tx_data = req->rx_data; + } // Clear the TX and RX FIFO spi->dma |= (MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CLR | MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CLR); + if (states[spi_num].drv_ssel) { + // Setup the slave select + spi->mode |= MXC_F_SPIMSS_REVA_MODE_SSV; // Assert a high on Slave Select, + // to get the line ready for active low later + } + return E_NO_ERROR; } @@ -223,6 +237,7 @@ void MXC_SPIMSS_RevA_Handler(mxc_spimss_reva_regs_t *spi) // From the IRQ int MXC_SPIMSS_RevA_MasterTrans(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req) { int error; + int spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t*) spi); if ((error = MXC_SPIMSS_RevA_TransSetup(spi, req, 1)) != E_NO_ERROR) { return error; @@ -230,16 +245,18 @@ int MXC_SPIMSS_RevA_MasterTrans(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t * req->callback = NULL; - spi->mode &= ~(MXC_F_SPIMSS_REVA_MODE_SSV); // This will assert the Slave Select. - spi->ctrl |= MXC_F_SPIMSS_REVA_CTRL_ENABLE; // Enable/Start SPI + spi->ctrl |= MXC_F_SPIMSS_REVA_CTRL_ENABLE; // Enable/Start SPI + if (states[spi_num].drv_ssel) { + spi->mode &= ~(MXC_F_SPIMSS_REVA_MODE_SSV); // This will assert the Slave Select. + } while (MXC_SPIMSS_RevA_MasterTransHandler(spi, req) != 0) {} - spi->mode |= MXC_F_SPIMSS_REVA_MODE_SSV; - - spi->ctrl &= - ~(MXC_F_SPIMSS_REVA_CTRL_ENABLE); // Last of the SPIMSS value has been transmitted... - // stop the transmission... + if (states[spi_num].drv_ssel) { + spi->mode |= MXC_F_SPIMSS_REVA_MODE_SSV; + } + spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_ENABLE); // Last of the SPIMSS value has been transmitted... + // stop the transmission... return E_NO_ERROR; } @@ -268,9 +285,7 @@ int MXC_SPIMSS_RevA_MasterTransAsync(mxc_spimss_reva_regs_t *spi, spimss_reva_re { int error; uint8_t int_enable; - - // Clear state for next transaction - MXC_SPIMSS_AbortAsync((mxc_spimss_req_t *)req); + int spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t*) spi); if ((error = MXC_SPIMSS_RevA_TransSetup(spi, req, 1)) != E_NO_ERROR) { return error; @@ -278,9 +293,10 @@ int MXC_SPIMSS_RevA_MasterTransAsync(mxc_spimss_reva_regs_t *spi, spimss_reva_re int_enable = MXC_SPIMSS_RevA_MasterTransHandler(spi, req); - spi->mode ^= MXC_F_SPIMSS_REVA_MODE_SSV; // This will assert the Slave Select. - - spi->ctrl |= MXC_F_SPIMSS_REVA_CTRL_ENABLE; // Enable/Start SPI + spi->ctrl |= MXC_F_SPIMSS_REVA_CTRL_ENABLE; // Enable/Start SPI + if (states[spi_num].drv_ssel) { + spi->mode ^= MXC_F_SPIMSS_REVA_MODE_SSV; // This will assert the Slave Select. + } if (int_enable == 1) { spi->ctrl |= (MXC_F_SPIMSS_REVA_CTRL_IRQE | MXC_F_SPIMSS_REVA_CTRL_STR); @@ -339,6 +355,10 @@ uint32_t MXC_SPIMSS_RevA_TransHandler(mxc_spimss_reva_regs_t *spi, spimss_reva_r spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t *)spi); + if (spi_num < 0) { + MXC_ASSERT(0); + } + // Read the RX FIFO if (req->rx_data != NULL) { // Wait for there to be data in the RX FIFO @@ -461,6 +481,15 @@ uint32_t MXC_SPIMSS_RevA_TransHandler(mxc_spimss_reva_regs_t *spi, spimss_reva_r return int_en; } +/* ************************************************************************* */ +int MXC_SPIMSS_RevA_SetDefaultTXData (spimss_reva_req_t* spi, unsigned int defaultTXData) +{ + int spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t*) spi); + MXC_ASSERT (spi_num >= 0); + states[spi_num].defaultTXData = defaultTXData; + return E_NO_ERROR; +} + /* ************************************************************************* */ int MXC_SPIMSS_RevA_AbortAsync(spimss_reva_req_t *req) { diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_reva.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_reva.h index a2d1cfd83c8e..5d179fefaed3 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_reva.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_reva.h @@ -95,13 +95,14 @@ struct spimss_reva_req { spimss_reva_callback_fn callback; /**< Callback function if desired, NULL otherwise */ }; -int MXC_SPIMSS_RevA_Init(mxc_spimss_reva_regs_t *spi, unsigned mode, unsigned freq); +int MXC_SPIMSS_RevA_Init(mxc_spimss_reva_regs_t *spi, unsigned mode, unsigned freq, unsigned drv_ssel); int MXC_SPIMSS_RevA_Shutdown(mxc_spimss_reva_regs_t *spi); void MXC_SPIMSS_RevA_Handler(mxc_spimss_reva_regs_t *spi); int MXC_SPIMSS_RevA_MasterTrans(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req); int MXC_SPIMSS_RevA_SlaveTrans(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req); int MXC_SPIMSS_RevA_MasterTransAsync(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req); int MXC_SPIMSS_RevA_SlaveTransAsync(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req); +int MXC_SPIMSS_RevA_SetDefaultTXData (spimss_reva_req_t* spi, unsigned int defaultTXData); int MXC_SPIMSS_RevA_AbortAsync(spimss_reva_req_t *req); #endif // LIBRARIES_PERIPHDRIVERS_SOURCE_SPIMSS_SPIMSS_REVA_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/mxc_lock.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/mxc_lock.c index 459df723f14a..734196f11a98 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/mxc_lock.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/mxc_lock.c @@ -35,6 +35,8 @@ #include "mxc_device.h" #include "mxc_lock.h" +#if USE_LOCK_IN_DRIVERS + #ifndef __riscv /* ************************************************************************** */ int MXC_GetLock(uint32_t *lock, uint32_t value) @@ -75,3 +77,5 @@ void MXC_FreeLock(uint32_t *lock) #warning "Unimplemented for RISCV" } #endif + +#endif // USE_LOCK_IN_DRIVERS \ No newline at end of file diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/pins_me11.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/pins_me11.c index 14be089aff08..a122971501e3 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/pins_me11.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/pins_me11.c @@ -67,18 +67,15 @@ const mxc_gpio_cfg_t gpio_cfg_uart1c = { MXC_GPIO0, (MXC_GPIO_PIN_6 | MXC_GPIO_P const mxc_gpio_cfg_t gpio_cfg_uart1_flow = { MXC_GPIO0, (MXC_GPIO_PIN_12 | MXC_GPIO_PIN_13), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE }; -const mxc_gpio_cfg_t gpio_cfg_spi0 = { - MXC_GPIO0, (MXC_GPIO_PIN_4 | MXC_GPIO_PIN_5 | MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7), - MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE -}; -const mxc_gpio_cfg_t gpio_cfg_spi1a = { - MXC_GPIO0, (MXC_GPIO_PIN_10 | MXC_GPIO_PIN_11 | MXC_GPIO_PIN_12 | MXC_GPIO_PIN_13), - MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE -}; -const mxc_gpio_cfg_t gpio_cfg_spi1b = { - MXC_GPIO0, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1 | MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3), - MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE -}; +//SPI0 +const mxc_gpio_cfg_t gpio_cfg_spi0 = { MXC_GPIO0, (MXC_GPIO_PIN_4 | MXC_GPIO_PIN_5 | MXC_GPIO_PIN_6), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_spi0_ss = { MXC_GPIO0, MXC_GPIO_PIN_7, MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE }; +// SPI1A +const mxc_gpio_cfg_t gpio_cfg_spi1a = { MXC_GPIO0, (MXC_GPIO_PIN_10| MXC_GPIO_PIN_11| MXC_GPIO_PIN_12), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_spi1a_ss = { MXC_GPIO0, MXC_GPIO_PIN_13, MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE }; +//SPI1B +const mxc_gpio_cfg_t gpio_cfg_spi1b = { MXC_GPIO0, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1 | MXC_GPIO_PIN_2), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_spi1b_ss = { MXC_GPIO0, MXC_GPIO_PIN_3, MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE }; // Timers are only defined once, depending on package, each timer could be mapped to other pins const mxc_gpio_cfg_t gpio_cfg_tmr0 = { MXC_GPIO0, MXC_GPIO_PIN_3, MXC_GPIO_FUNC_ALT3, diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/lp_ticker.c b/targets/TARGET_Maxim/TARGET_MAX32660/lp_ticker.c index 315352b172c9..864d27b016a8 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/lp_ticker.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/lp_ticker.c @@ -162,9 +162,7 @@ void lp_ticker_init(void) unsigned int count; cfg.pres = LP_TIMER_PRESCALE; - cfg.mode = TMR_MODE_COMPARE; - cfg.bitMode = TMR_BIT_MODE_32; - cfg.clock = MXC_TMR_HFIO_CLK; + cfg.mode = TMR_MODE_COMPARE; cfg.cmp_cnt = 0;//MXC_TMR_GetCompare(LP_TIMER); cfg.pol = 0; diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/us_ticker.c b/targets/TARGET_Maxim/TARGET_MAX32660/us_ticker.c index 539751c609a6..daa15bcaa709 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/us_ticker.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/us_ticker.c @@ -49,9 +49,7 @@ void us_ticker_init(void) unsigned int count; cfg.pres = US_TIMER_PRESCALE; - cfg.mode = TMR_MODE_COMPARE; - cfg.bitMode = TMR_BIT_MODE_32; - cfg.clock = MXC_TMR_HFIO_CLK; + cfg.mode = TMR_MODE_COMPARE; cfg.cmp_cnt = 0;//MXC_TMR_GetCompare(US_TIMER); cfg.pol = 0;