diff --git a/CMSIS/RTOS2/RTX/Source/IAR/irq_ca.s b/CMSIS/RTOS2/RTX/Source/IAR/irq_ca.s
index acb2b12344..6c363e37a0 100644
--- a/CMSIS/RTOS2/RTX/Source/IAR/irq_ca.s
+++ b/CMSIS/RTOS2/RTX/Source/IAR/irq_ca.s
@@ -42,7 +42,6 @@ TCB_SP_OFS      EQU      56                         ; osRtxThread_t.sp offset
 
 
                 PRESERVE8
-                ARM
 
 
                 SECTION .rodata:DATA:NOROOT(2)
@@ -370,19 +369,19 @@ osRtxContextSave
 
                 VMRS    R2, FPSCR
                 STMDB   R3!, {R2,R12}               ; Push FPSCR, maintain 8-byte alignment
-                IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 16
+#if (TARGET_FEATURE_EXTENSION_REGISTER_COUNT == 16)
                 VSTMDB  R3!, {D0-D15}
                 LDRB    R2, [R0, #TCB_SP_FRAME]     ; Record in TCB that VFP/D16 state is stacked
                 ORR     R2, R2, #2
                 STRB    R2, [R0, #TCB_SP_FRAME]
-                ENDIF
-                IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32
+#endif
+#if (TARGET_FEATURE_EXTENSION_REGISTER_COUNT == 32)
                 VSTMDB  R3!, {D0-D15}
                 VSTMDB  R3!, {D16-D31}
                 LDRB    R2, [R0, #TCB_SP_FRAME]     ; Record in TCB that NEON/D32 state is stacked
                 ORR     R2, R2, #4
                 STRB    R2, [R0, #TCB_SP_FRAME]
-                ENDIF
+#endif
 
 osRtxContextSave1
                 STR     R3, [R0, #TCB_SP_OFS]       ; Store user sp to osRtxInfo.thread.run.curr
@@ -399,9 +398,9 @@ osRtxContextRestore
                 MCR     p15, 0, R2, c1, c0, 2       ; Write CPACR
                 BEQ     osRtxContextRestore1        ; No VFP
                 ISB                                 ; Only sync if we enabled VFP, otherwise we will context switch before next VFP instruction anyway
-                IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32
+#if (TARGET_FEATURE_EXTENSION_REGISTER_COUNT == 32)
                 VLDMIA  R3!, {D16-D31}
-                ENDIF
+#endif
                 VLDMIA  R3!, {D0-D15}
                 LDR     R2, [R3]
                 VMSR    FPSCR, R2
diff --git a/CMSIS/RTOS2/RTX/Source/rtx_core_ca.h b/CMSIS/RTOS2/RTX/Source/rtx_core_ca.h
index f3a7a2addc..0f9109fae9 100644
--- a/CMSIS/RTOS2/RTX/Source/rtx_core_ca.h
+++ b/CMSIS/RTOS2/RTX/Source/rtx_core_ca.h
@@ -78,8 +78,10 @@ __STATIC_INLINE uint32_t __get_PSP (void) {
   register uint32_t ret;
 
   __asm volatile (
+#if !defined ( __ICCARM__ )
     ".syntax unified\n\t"
     ".arm\n\t"
+#endif
     "sub  sp,sp,#4\n\t"
     "stm  sp,{sp}^\n\t"
     "pop  {%[ret]}\n\t"