From c1dbf04ad96ce314363fb772b4a502a3d117968b Mon Sep 17 00:00:00 2001
From: ua1arn <mgs2001@mail.ru>
Date: Tue, 3 Mar 2020 11:36:07 +0300
Subject: [PATCH] Irq modes handling

Change-Id: I427af99ad6c561619068155c1e52fe4081282785
---
 CMSIS/Core_A/Include/irq_ctrl.h    | 12 +++++++++---
 CMSIS/Core_A/Source/irq_ctrl_gic.c | 14 +++++++++++---
 2 files changed, 20 insertions(+), 6 deletions(-)

diff --git a/CMSIS/Core_A/Include/irq_ctrl.h b/CMSIS/Core_A/Include/irq_ctrl.h
index b171ef0add..1ca29a27e9 100644
--- a/CMSIS/Core_A/Include/irq_ctrl.h
+++ b/CMSIS/Core_A/Include/irq_ctrl.h
@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     irq_ctrl.h
  * @brief    Interrupt Controller API header file
- * @version  V1.0.0
- * @date     23. June 2017
+ * @version  V1.1.0
+ * @date     03. March 2020
  ******************************************************************************/
 /*
- * Copyright (c) 2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2017-2020 ARM Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -78,6 +78,12 @@ typedef int32_t IRQn_ID_t;
 #define IRQ_MODE_CPU_6              (0x40UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 6
 #define IRQ_MODE_CPU_7              (0x80UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 7
 
+// Encoding in some early GIC implementations
+#define IRQ_MODE_MODEL_Pos          (13U)
+#define IRQ_MODE_MODEL_Msk          (0x1UL << IRQ_MODE_MODEL_Pos)
+#define IRQ_MODE_MODEL_NN           (0x0UL << IRQ_MODE_MODEL_Pos)     ///< Corresponding interrupt is handled using the N-N model
+#define IRQ_MODE_MODEL_1N           (0x1UL << IRQ_MODE_MODEL_Pos)     ///< Corresponding interrupt is handled using the 1-N model
+
 #define IRQ_MODE_ERROR              (0x80000000UL)                    ///< Bit indicating mode value error
 
 /* Interrupt priority bit-masks */
diff --git a/CMSIS/Core_A/Source/irq_ctrl_gic.c b/CMSIS/Core_A/Source/irq_ctrl_gic.c
index 25d1359159..e60467099e 100644
--- a/CMSIS/Core_A/Source/irq_ctrl_gic.c
+++ b/CMSIS/Core_A/Source/irq_ctrl_gic.c
@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     irq_ctrl_gic.c
  * @brief    Interrupt controller handling implementation for GIC
- * @version  V1.0.1
- * @date     9. April 2018
+ * @version  V1.1.0
+ * @date     03. March 2020
  ******************************************************************************/
 /*
- * Copyright (c) 2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2017-2020 ARM Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -148,6 +148,11 @@ __WEAK int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode) {
       status = -1;
     }
 
+    val = (mode & IRQ_MODE_MODEL_Msk);
+    if (val == IRQ_MODE_MODEL_1N) {
+      cfg |= 1;   // 1-N model
+    }
+
     // Check interrupt type
     val = mode & IRQ_MODE_TYPE_Msk;
 
@@ -216,6 +221,9 @@ __WEAK uint32_t IRQ_GetMode (IRQn_ID_t irqn) {
       mode |= IRQ_MODE_TRIG_LEVEL;
     }
 
+    if (val & 1U) {
+      mode |= IRQ_MODE_MODEL_1N;
+    }
     // Get interrupt CPU targets
     mode |= GIC_GetTarget ((IRQn_Type)irqn) << IRQ_MODE_CPU_Pos;