From b91922ab72c166a3522bb191814b081c426f1ebc Mon Sep 17 00:00:00 2001 From: Jonatan Antoni Date: Tue, 17 Oct 2017 16:37:14 +0200 Subject: [PATCH] Core: Fixed inline functions to use consistent code style. --- CMSIS/Core/Include/cmsis_armcc.h | 20 ++- CMSIS/Core/Include/cmsis_armclang.h | 23 ++-- CMSIS/Core/Include/cmsis_gcc.h | 23 ++-- CMSIS/Core/Include/cmsis_iccarm.h | 175 +++++++++++++++++--------- CMSIS/Core_A/Include/cmsis_armcc.h | 12 +- CMSIS/Core_A/Include/cmsis_armclang.h | 3 +- CMSIS/Core_A/Include/cmsis_gcc.h | 18 ++- CMSIS/Core_A/Include/cmsis_iccarm.h | 27 ++-- 8 files changed, 203 insertions(+), 98 deletions(-) diff --git a/CMSIS/Core/Include/cmsis_armcc.h b/CMSIS/Core/Include/cmsis_armcc.h index 246ac03c30..b127d2f4e9 100644 --- a/CMSIS/Core/Include/cmsis_armcc.h +++ b/CMSIS/Core/Include/cmsis_armcc.h @@ -737,12 +737,16 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3 */ __attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) { - if ((sat >= 1U) && (sat <= 32U)) { + if ((sat >= 1U) && (sat <= 32U)) + { const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); const int32_t min = -1 - max ; - if (val > max) { + if (val > max) + { return max; - } else if (val < min) { + } + else if (val < min) + { return min; } } @@ -758,11 +762,15 @@ __attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint3 */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) { - if (sat <= 31U) { + if (sat <= 31U) + { const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) { + if (val > (int32_t)max) + { return max; - } else if (val < 0) { + } + else if (val < 0) + { return 0U; } } diff --git a/CMSIS/Core/Include/cmsis_armclang.h b/CMSIS/Core/Include/cmsis_armclang.h index a0e3d67d12..f6654764a0 100644 --- a/CMSIS/Core/Include/cmsis_armclang.h +++ b/CMSIS/Core/Include/cmsis_armclang.h @@ -822,7 +822,8 @@ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) { op2 %= 32U; - if (op2 == 0U) { + if (op2 == 0U) + { return op1; } return (op1 >> op2) | (op1 << (32U - op2)); @@ -1065,12 +1066,16 @@ __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) */ __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) { - if ((sat >= 1U) && (sat <= 32U)) { + if ((sat >= 1U) && (sat <= 32U)) + { const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); const int32_t min = -1 - max ; - if (val > max) { + if (val > max) + { return max; - } else if (val < min) { + } + else if (val < min) + { return min; } } @@ -1086,11 +1091,15 @@ __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) */ __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) { - if (sat <= 31U) { + if (sat <= 31U) + { const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) { + if (val > (int32_t)max) + { return max; - } else if (val < 0) { + } + else if (val < 0) + { return 0U; } } diff --git a/CMSIS/Core/Include/cmsis_gcc.h b/CMSIS/Core/Include/cmsis_gcc.h index a0ab406e93..73e197061f 100644 --- a/CMSIS/Core/Include/cmsis_gcc.h +++ b/CMSIS/Core/Include/cmsis_gcc.h @@ -895,7 +895,8 @@ __STATIC_FORCEINLINE int16_t __REVSH(int16_t value) __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) { op2 %= 32U; - if (op2 == 0U) { + if (op2 == 0U) + { return op1; } return (op1 >> op2) | (op1 << (32U - op2)); @@ -1238,12 +1239,16 @@ __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) */ __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) { - if ((sat >= 1U) && (sat <= 32U)) { + if ((sat >= 1U) && (sat <= 32U)) + { const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); const int32_t min = -1 - max ; - if (val > max) { + if (val > max) + { return max; - } else if (val < min) { + } + else if (val < min) + { return min; } } @@ -1259,11 +1264,15 @@ __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) */ __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) { - if (sat <= 31U) { + if (sat <= 31U) + { const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) { + if (val > (int32_t)max) + { return max; - } else if (val < 0) { + } + else if (val < 0) + { return 0U; } } diff --git a/CMSIS/Core/Include/cmsis_iccarm.h b/CMSIS/Core/Include/cmsis_iccarm.h index c5aab87979..f848905d00 100644 --- a/CMSIS/Core/Include/cmsis_iccarm.h +++ b/CMSIS/Core/Include/cmsis_iccarm.h @@ -161,7 +161,8 @@ #ifndef __UNALIGNED_UINT16_READ #pragma language=save #pragma language=extended -__IAR_FT uint16_t __iar_uint16_read(void const *ptr) { +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ return *(__packed uint16_t*)(ptr); } #pragma language=restore @@ -172,7 +173,8 @@ __IAR_FT uint16_t __iar_uint16_read(void const *ptr) { #ifndef __UNALIGNED_UINT16_WRITE #pragma language=save #pragma language=extended -__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) { +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ *(__packed uint16_t*)(ptr) = val;; } #pragma language=restore @@ -182,7 +184,8 @@ __IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) { #ifndef __UNALIGNED_UINT32_READ #pragma language=save #pragma language=extended -__IAR_FT uint32_t __iar_uint32_read(void const *ptr) { +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ return *(__packed uint32_t*)(ptr); } #pragma language=restore @@ -192,7 +195,8 @@ __IAR_FT uint32_t __iar_uint32_read(void const *ptr) { #ifndef __UNALIGNED_UINT32_WRITE #pragma language=save #pragma language=extended -__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) { +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ *(__packed uint32_t*)(ptr) = val;; } #pragma language=restore @@ -324,7 +328,8 @@ __packed struct __iar_u32 { uint32_t v; }; #define __REV __iar_builtin_REV #define __REV16 __iar_builtin_REV16 - __IAR_FT int16_t __REVSH(int16_t val) { + __IAR_FT int16_t __REVSH(int16_t val) + { return (int16_t) __iar_builtin_REVSH(val); } @@ -441,8 +446,9 @@ __packed struct __iar_u32 { uint32_t v; }; #undef __RBIT #undef __get_APSR - __STATIC_INLINE uint8_t __CLZ(uint32_t data) { - if (data == 0u) { return 32u; } + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } uint32_t count = 0U; uint32_t mask = 0x80000000U; @@ -455,7 +461,8 @@ __packed struct __iar_u32 { uint32_t v; }; return count; } - __STATIC_INLINE uint32_t __RBIT(uint32_t v) { + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { uint8_t sc = 31U; uint32_t r = v; for (v >>= 1U; v; v >>= 1U) @@ -467,7 +474,8 @@ __packed struct __iar_u32 { uint32_t v; }; return (r << sc); } - __STATIC_INLINE uint32_t __get_APSR(void) { + __STATIC_INLINE uint32_t __get_APSR(void) + { uint32_t res; __asm("MRS %0,APSR" : "=r" (res)); return res; @@ -494,11 +502,13 @@ __packed struct __iar_u32 { uint32_t v; }; #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) - __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) { + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { return __LDREX((unsigned long *)ptr); } - __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) { + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { return __STREX(value, (unsigned long *)ptr); } #endif @@ -507,13 +517,15 @@ __packed struct __iar_u32 { uint32_t v; }; /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ #if (__CORTEX_M >= 0x03) - __IAR_FT uint32_t __RRX(uint32_t value) { + __IAR_FT uint32_t __RRX(uint32_t value) + { uint32_t result; __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); return(result); } - __IAR_FT void __set_BASEPRI_MAX(uint32_t value) { + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); } @@ -524,98 +536,117 @@ __packed struct __iar_u32 { uint32_t v; }; #endif /* (__CORTEX_M >= 0x03) */ - __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) { + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); } #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) { + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { uint32_t res; __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); return res; } - __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) { + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); } - __IAR_FT uint32_t __TZ_get_PSP_NS(void) { + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { uint32_t res; __asm volatile("MRS %0,PSP_NS" : "=r" (res)); return res; } - __IAR_FT void __TZ_set_PSP_NS(uint32_t value) { + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { __asm volatile("MSR PSP_NS,%0" :: "r" (value)); } - __IAR_FT uint32_t __TZ_get_MSP_NS(void) { + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { uint32_t res; __asm volatile("MRS %0,MSP_NS" : "=r" (res)); return res; } - __IAR_FT void __TZ_set_MSP_NS(uint32_t value) { + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { __asm volatile("MSR MSP_NS,%0" :: "r" (value)); } - __IAR_FT uint32_t __TZ_get_SP_NS(void) { + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { uint32_t res; __asm volatile("MRS %0,SP_NS" : "=r" (res)); return res; } - __IAR_FT void __TZ_set_SP_NS(uint32_t value) { + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { __asm volatile("MSR SP_NS,%0" :: "r" (value)); } - __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) { + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { uint32_t res; __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); return res; } - __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) { + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); } - __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) { + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { uint32_t res; __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); return res; } - __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) { + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); } - __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) { + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { uint32_t res; __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); return res; } - __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) { + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); } - __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) { + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { uint32_t res; __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); return res; } - __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) { + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); } - __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) { + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { uint32_t res; __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); return res; } - __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) { + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); } @@ -626,25 +657,35 @@ __packed struct __iar_u32 { uint32_t v; }; #define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) #if __IAR_M0_FAMILY - __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) { - if ((sat >= 1U) && (sat <= 32U)) { + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); const int32_t min = -1 - max ; - if (val > max) { + if (val > max) + { return max; - } else if (val < min) { + } + else if (val < min) + { return min; } } return val; } - __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) { - if (sat <= 31U) { + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) { + if (val > (int32_t)max) + { return max; - } else if (val < 0) { + } + else if (val < 0) + { return 0U; } } @@ -654,33 +695,39 @@ __packed struct __iar_u32 { uint32_t v; }; #if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ - __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) { + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { uint32_t res; __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); return ((uint8_t)res); } - __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) { + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { uint32_t res; __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); return ((uint16_t)res); } - __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) { + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { uint32_t res; __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); return res; } - __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) { + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); } - __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) { + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); } - __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) { + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); } @@ -690,67 +737,79 @@ __packed struct __iar_u32 { uint32_t v; }; (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) { + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { uint32_t res; __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); return ((uint8_t)res); } - __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) { + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { uint32_t res; __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); return ((uint16_t)res); } - __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) { + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { uint32_t res; __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); return res; } - __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) { + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { __ASM volatile ("STLB %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); } - __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) { + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { __ASM volatile ("STLH %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); } - __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) { + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { __ASM volatile ("STL %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); } - __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) { + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { uint32_t res; __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); return ((uint8_t)res); } - __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) { + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { uint32_t res; __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); return ((uint16_t)res); } - __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) { + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { uint32_t res; __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); return res; } - __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) { + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { uint32_t res; __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); return res; } - __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) { + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { uint32_t res; __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); return res; } - __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) { + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { uint32_t res; __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); return res; diff --git a/CMSIS/Core_A/Include/cmsis_armcc.h b/CMSIS/Core_A/Include/cmsis_armcc.h index dbbe3e139d..c0b61a7cdb 100644 --- a/CMSIS/Core_A/Include/cmsis_armcc.h +++ b/CMSIS/Core_A/Include/cmsis_armcc.h @@ -354,14 +354,16 @@ __STATIC_INLINE void __set_CPSR(uint32_t cpsr) /** \brief Get Mode \return Processor Mode */ -__STATIC_INLINE uint32_t __get_mode(void) { +__STATIC_INLINE uint32_t __get_mode(void) +{ return (__get_CPSR() & 0x1FU); } /** \brief Set Mode \param [in] mode Mode value to set */ -__STATIC_INLINE __ASM void __set_mode(uint32_t mode) { +__STATIC_INLINE __ASM void __set_mode(uint32_t mode) +{ MOV r1, lr MSR CPSR_C, r0 BX r1 @@ -467,7 +469,8 @@ __STATIC_INLINE void __set_FPEXC(uint32_t fpexc) /** \brief Clean and Invalidate the entire data or unified cache * \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean */ -__STATIC_INLINE __ASM void __L1C_CleanInvalidateCache(uint32_t op) { +__STATIC_INLINE __ASM void __L1C_CleanInvalidateCache(uint32_t op) +{ ARM PUSH {R4-R11} @@ -526,7 +529,8 @@ Finished Critical section, called from undef handler, so systick is disabled */ -__STATIC_INLINE __ASM void __FPU_Enable(void) { +__STATIC_INLINE __ASM void __FPU_Enable(void) +{ ARM //Permit access to VFP/NEON, registers by modifying CPACR diff --git a/CMSIS/Core_A/Include/cmsis_armclang.h b/CMSIS/Core_A/Include/cmsis_armclang.h index 615b1b6d12..1d2efc9860 100644 --- a/CMSIS/Core_A/Include/cmsis_armclang.h +++ b/CMSIS/Core_A/Include/cmsis_armclang.h @@ -184,7 +184,8 @@ __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) { op2 %= 32U; - if (op2 == 0U) { + if (op2 == 0U) + { return op1; } return (op1 >> op2) | (op1 << (32U - op2)); diff --git a/CMSIS/Core_A/Include/cmsis_gcc.h b/CMSIS/Core_A/Include/cmsis_gcc.h index 776f3c9f83..0ba6d8ca97 100644 --- a/CMSIS/Core_A/Include/cmsis_gcc.h +++ b/CMSIS/Core_A/Include/cmsis_gcc.h @@ -502,14 +502,16 @@ __ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory"); /** \brief Get Mode \return Processor Mode */ -__STATIC_FORCEINLINE uint32_t __get_mode(void) { +__STATIC_FORCEINLINE uint32_t __get_mode(void) +{ return (__get_CPSR() & 0x1FU); } /** \brief Set Mode \param [in] mode Mode value to set */ -__STATIC_FORCEINLINE void __set_mode(uint32_t mode) { +__STATIC_FORCEINLINE void __set_mode(uint32_t mode) +{ __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); } @@ -629,8 +631,10 @@ __STATIC_INLINE void __L1C_MaintainDCacheSetWay(uint32_t level, uint32_t maint) log2_linesize = (ccsidr & 0x00000007) + 2 + 2; log2_num_ways = log2_up(num_ways); shift_way = 32 - log2_num_ways; - for(int way = num_ways-1; way >= 0; way--) { - for(int set = num_sets-1; set >= 0; set--) { + for(int way = num_ways-1; way >= 0; way--) + { + for(int set = num_sets-1; set >= 0; set--) + { Dummy = (level << 1) | (set << log2_linesize) | (way << shift_way); switch (maint) { @@ -656,7 +660,8 @@ __STATIC_INLINE void __L1C_MaintainDCacheSetWay(uint32_t level, uint32_t maint) Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency */ -__STATIC_INLINE void __L1C_CleanInvalidateCache(uint32_t op) { +__STATIC_INLINE void __L1C_CleanInvalidateCache(uint32_t op) +{ register volatile uint32_t clidr; uint32_t cache_type; clidr = __get_CLIDR(); @@ -675,7 +680,8 @@ __STATIC_INLINE void __L1C_CleanInvalidateCache(uint32_t op) { Critical section, called from undef handler, so systick is disabled */ -__STATIC_INLINE void __FPU_Enable(void) { +__STATIC_INLINE void __FPU_Enable(void) +{ __ASM volatile( //Permit access to VFP/NEON, registers by modifying CPACR " MRC p15,0,R1,c1,c0,2 \n" diff --git a/CMSIS/Core_A/Include/cmsis_iccarm.h b/CMSIS/Core_A/Include/cmsis_iccarm.h index f87ecda779..f85b324dda 100644 --- a/CMSIS/Core_A/Include/cmsis_iccarm.h +++ b/CMSIS/Core_A/Include/cmsis_iccarm.h @@ -123,7 +123,8 @@ #ifndef __UNALIGNED_UINT16_READ #pragma language=save #pragma language=extended - __IAR_FT uint16_t __iar_uint16_read(void const *ptr) { + __IAR_FT uint16_t __iar_uint16_read(void const *ptr) + { return *(__packed uint16_t*)(ptr); } #pragma language=restore @@ -134,7 +135,8 @@ #ifndef __UNALIGNED_UINT16_WRITE #pragma language=save #pragma language=extended - __IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) { + __IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) + { *(__packed uint16_t*)(ptr) = val;; } #pragma language=restore @@ -144,7 +146,8 @@ #ifndef __UNALIGNED_UINT32_READ #pragma language=save #pragma language=extended - __IAR_FT uint32_t __iar_uint32_read(void const *ptr) { + __IAR_FT uint32_t __iar_uint32_read(void const *ptr) + { return *(__packed uint32_t*)(ptr); } #pragma language=restore @@ -154,7 +157,8 @@ #ifndef __UNALIGNED_UINT32_WRITE #pragma language=save #pragma language=extended - __IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) { + __IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) + { *(__packed uint32_t*)(ptr) = val;; } #pragma language=restore @@ -268,7 +272,8 @@ #define __REV __iar_builtin_REV #define __REV16 __iar_builtin_REV16 - __IAR_FT int16_t __REVSH(int16_t val) { + __IAR_FT int16_t __REVSH(int16_t val) + { return (int16_t) __iar_builtin_REVSH(val); } @@ -379,23 +384,27 @@ __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); } - __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) { + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { return __LDREX((unsigned long *)ptr); } - __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) { + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { return __STREX(value, (unsigned long *)ptr); } - __IAR_FT uint32_t __RRX(uint32_t value) { + __IAR_FT uint32_t __RRX(uint32_t value) + { uint32_t result; __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); return(result); } - __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) { + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); }