From 51f8f89612c8330c0116479cfe3a2cb04c390e2b Mon Sep 17 00:00:00 2001
From: RoboSchmied <github@roboschmie.de>
Date: Thu, 28 Mar 2024 09:02:55 +0100
Subject: [PATCH] Fix: typos in doc

Signed-off-by: RoboSchmied <github@roboschmie.de>
---
 CMSIS/DoxyGen/SVD/src/svd.txt         | 2 +-
 CMSIS/DoxyGen/Zone/src/XML_Format.txt | 2 +-
 CMSIS/Utilities/CMSIS-SVD.xsd         | 4 ++--
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/CMSIS/DoxyGen/SVD/src/svd.txt b/CMSIS/DoxyGen/SVD/src/svd.txt
index 461f87df74..69fe6d8a9b 100644
--- a/CMSIS/DoxyGen/SVD/src/svd.txt
+++ b/CMSIS/DoxyGen/SVD/src/svd.txt
@@ -526,7 +526,7 @@ Data Check Errors
   <tr><td>M323</td> <td>WARNING</td><td>\em 'LEVEL' \<\em 'ITEM'> \em 'NAME' contains text \em 'TEXT'</td><td></td></tr>             
   <tr><td>M324</td> <td>ERROR</td><td>Field \em 'NAME' \em 'BITRANGE' does not fit into Register \em 'NAME2':\em 'NUM' \em 'LINE'</td><td></td></tr>
   <tr><td>M325</td> <td>ERROR</td><td>CPU Revision is not set"</td><td></td></tr>                                                   
-  <tr><td>M326</td> <td>ERROR</td><td>Endianess is not set, using default (little)</td><td></td></tr>                         
+  <tr><td>M326</td> <td>ERROR</td><td>Endianness is not set, using default (little)</td><td></td></tr>                         
   <tr><td>M327</td> <td>ERROR</td><td>NVIC Prio Bits not set or wrong value, must be 2..8. Using default (4)</td><td></td></tr>
   <tr><td>M328</td> <td>WARNING</td><td>\em 'LEVEL' \em 'NAME' has no Registers, ignoring \em 'LEVEL'.</td><td></td></tr>                 
   <tr><td>M329</td> <td>ERROR</td><td>CPU Type is not set, using default (Cortex-M3)</td><td></td></tr>                         
diff --git a/CMSIS/DoxyGen/Zone/src/XML_Format.txt b/CMSIS/DoxyGen/Zone/src/XML_Format.txt
index 357d2332a7..9ae0bf729e 100644
--- a/CMSIS/DoxyGen/Zone/src/XML_Format.txt
+++ b/CMSIS/DoxyGen/Zone/src/XML_Format.txt
@@ -445,7 +445,7 @@ The information in this element is identical with CMSIS-Pack, except that it pro
   </tr>
   <tr>
     <td>Dendian</td>
-    <td>Specifies the endianess of the processor.</td>
+    <td>Specifies the endianness of the processor.</td>
     <td>DendianEnum</td>
     <td>required</td>
   </tr>
diff --git a/CMSIS/Utilities/CMSIS-SVD.xsd b/CMSIS/Utilities/CMSIS-SVD.xsd
index 352e18485d..817962afb1 100644
--- a/CMSIS/Utilities/CMSIS-SVD.xsd
+++ b/CMSIS/Utilities/CMSIS-SVD.xsd
@@ -128,7 +128,7 @@
       <xs:pattern value="r[0-9]*p[0-9]*"/>
     </xs:restriction>
   </xs:simpleType>
-  <!-- EndianType pre-defines the tokens for specifying the endianess of the device -->
+  <!-- EndianType pre-defines the tokens for specifying the endianness of the device -->
   <xs:simpleType name="endianType">
     <xs:restriction base="xs:token">
       <xs:enumeration value="little"/>
@@ -345,7 +345,7 @@
       <xs:element name="name" type="cpuNameType"/>
       <!-- V1.1: ARM defined revision of the cpu -->
       <xs:element name="revision" type="revisionType"/>
-      <!-- V1.1: Endian specifies the endianess of the processor/device -->
+      <!-- V1.1: Endian specifies the endianness of the processor/device -->
       <xs:element name="endian" type="endianType"/>
       <!-- V1.1: mpuPresent specifies whether or not a memory protection unit is physically present -->
       <xs:element name="mpuPresent" type="xs:boolean" minOccurs="0"/>